Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the present disclosure includes: providing a substrate, the substrate being provided with first trenches arranged in a same direction; forming protective layers on side walls of the first trenches; forming second trenches at bottoms of the first trenches, the second trenches being wider than the first trenches; forming first spacers on side walls of the second trenches to reduce opening sizes of the second trenches; filling the first trenches and the second trenches to form second spacers, and forming voids in the second trenches; forming third trenches in the substrate, the third trenches being perpendicular to the first trenches; and forming bit lines in the third trenches.

A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

An approach for creating a buried local interconnect around a DDB (double diffusion break) to reduce parasitic capacitance on a semiconductor device is disclosed. The approach utilizes a metal, as the local interconnect, buried in a cavity around the DDB region of a semiconductor substrate. The metal is disposed by two dielectric layers and the substrate. The two dielectric layers are recessed beneath two gate spacers. The buried local interconnect is recessed into the cavity where the top surface of the interconnect is situated below the top surface of the surrounding S/D (source/drain) epi (epitaxy). The metal of the local interconnect can be made from W, Ru or Co.

Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode, a first electrode, a first via and a second via. The substrate has a first surface and a second surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap exceeding that of the first nitride semiconductor layer. The gate electrode and the first electrode are disposed on the second nitride semiconductor layer. The first via extends from the second surface and is electrically connected to the first electrode. The second via extends from the second surface. The depth of the first via is different from the depth of the second via.

An electrode structure can include: a semiconductor substrate; a trench extending from an upper surface of the semiconductor substrate into the semiconductor substrate; a contact region extending from the upper surface of the semiconductor substrate into the semiconductor substrate; and filling material in the trench, wherein the contact area is in contact with outer sidewalls of the trench.

In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

A semiconductor device includes a semiconductor layer, a source region and a drain region that are formed in the semiconductor layer and at an interval in a first direction, a gate insulating film that is formed such as to cover a channel region between the source region and the drain region, and a gate electrode that is formed on the gate insulating film and opposes the channel region across the gate insulating film. The gate insulating film has a major portion on which the gate electrode is formed and extension portions projecting outward from each of both sides of the major portion in a second direction orthogonal to the first direction and leak current suppressing electrodes are formed on the extension portions.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate and directly contacting a bottom surface of the first source/drain feature.