A semiconductor device of an embodiment includes an element region and a termination region surrounding the element region. The element region includes a gate trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type on the first silicon carbide region, a third silicon carbide region of n-type on the second silicon carbide region, and a fourth silicon carbide region of p-type sandwiches the first silicon carbide region and the second silicon carbide region with the gate trench, the fourth silicon carbide region being deeper than the gate trench. The termination region includes a first trench surrounding the element region, and a fifth silicon carbide region of p-type between the first trench and the first silicon carbide region, the fifth silicon carbide region same or shallower than the fourth silicon carbide region. The semiconductor device includes a gate electrode, a first electrode, and a second electrode.

A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p.sup.−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p.sup.+-type extension and the innermost one of the p.sup.−−-type regions, at a position overlapping a border between the p.sup.+-type extension and the innermost one of the p.sup.−−-type regions. The FLRs are formed concurrently with p.sup.++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p.sup.++-type contact regions. An n.sup.+-type channel stopper region is formed concurrently with n.sup.+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n.sup.+-type source regions.

The present application discloses an SiC MOSFET device, including an SiC epitaxial layer in which a trench gate is formed, wherein a first bottom doped region is formed below a bottom surface of a gate trench, a second deep doped region with spacing from the gate trench is formed in the SiC epitaxial layer, the first bottom doped region is connected to a source so that voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by gate-source voltage; the second deep doped region extends downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region is located below a bottom surface of the first bottom doped region; a top of the second deep doped region is connected to the source. The present application further discloses a method for manufacturing an SiC MOSFET device.

An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer in contact with the first mask, and implanting a shallow well region in the drift region using the first mask and the spacer. A disclosed FET includes a drift region, a shallow well region, a deep well region located between the shallow well region and the drift region, and a junction field effect region: in contact with the shallow well region, the drift region, and the deep well region; and having a junction field effect doping concentration of the first conductivity type. The FETs can include a hybrid channel formed by a portion of the junction field effect region, as influenced by the deep well region, and the shallow well region.

A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.

In an example, a first hard mask is formed on a first surface of a semiconductor body, wherein first openings in the first hard mask expose first surface sections and second openings in the first hard mask expose second surface sections. First dopants of a first conductivity type are implanted selectively through the first openings into the semiconductor body. Second dopants of a second conductivity type are implanted selectively through the second openings into the semiconductor body. The second conductivity type is complementary to the first conductivity type. A second hard mask is formed that covers the first surface sections and the second surface sections, wherein third openings in the second hard mask expose third surface sections and fourth openings in the second hard mask expose fourth surface sections. Third dopants of the first conductivity type are implanted selectively through the third openings into the semiconductor body. Fourth dopants of the second conductivity type are implanted selectively through the fourth openings into the semiconductor body.

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.