A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.

An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.

Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n.sup. type drift region and not penetrating a SiC substrate; an n.sup.+ type side surface diffusion region formed on each side surface of the first trench; an n.sup.+ type bottom diffusion region formed under the n.sup. type drift region and in contact with the n.sup.+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n.sup. type drift region at regular spacings of 0.4 m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

A semiconductor device includes a semiconductor base body, and a first main electrode and a second main electrode provided on the semiconductor base body. The semiconductor base body includes a drift region of a first conductivity type through which a main current flows, a column region of a second conductivity type arranged adjacent to the drift region in parallel to a current passage of the main current, a second electrode-connection region of the first conductivity type electrically connected to the second main electrode, and a low-density electric-field relaxation region of the first conductivity type having a lower impurity concentration than the drift region and arranged between the second electrode-connection region and the column region.

Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p.sup.??-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p.sup.+-type extension and the innermost one of the p.sup.??-type regions, at a position overlapping a border between the p.sup.+-type extension and the innermost one of the p.sup.??-type regions. The FLRs are formed concurrently with p.sup.++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p.sup.++-type contact regions. An n.sup.+-type channel stopper region is formed concurrently with n.sup.+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n.sup.+-type source regions.

A semiconductor device includes n-type drift layer, n-type current spreading layer having higher impurity concentration than the drift layer, p-type base region provided on top surface, p-type gate-bottom protection region located in the current spreading layer, having first bottom edge portion formed of curved surface, p-type base-bottom embedded region in contact with bottom surface of the base region, having second bottom edge portion formed of curved surface on side surface facing the gate-bottom protection region, being separated from the gate-bottom protection region, and insulated gate electrode structure provided in trench penetrating through the base region to reach the gate-bottom protection region. Bottom surface of the base-bottom embedded region is deeper than bottom surface of the gate-bottom protection region, and minimum value of curvature radius of the first bottom edge portion is larger than minimum value of curvature radius of the second bottom edge portion.

In an example, a first hard mask is formed on a first surface of a semiconductor body, wherein first openings in the first hard mask expose first surface sections and second openings in the first hard mask expose second surface sections. First dopants of a first conductivity type are implanted selectively through the first openings into the semiconductor body. Second dopants of a second conductivity type are implanted selectively through the second openings into the semiconductor body. The second conductivity type is complementary to the first conductivity type. A second hard mask is formed that covers the first surface sections and the second surface sections, wherein third openings in the second hard mask expose third surface sections and fourth openings in the second hard mask expose fourth surface sections. Third dopants of the first conductivity type are implanted selectively through the third openings into the semiconductor body. Fourth dopants of the second conductivity type are implanted selectively through the fourth openings into the semiconductor body.