A method for producing a semiconductor device includes forming a gate electrode, a source electrode, and a drain electrode on an upper surface of a semiconductor layer, forming a first insulating film on the gate electrode, and forming a field plate on the first insulating film, the field plate having a first metal layer and a second metal layer having a higher Mohs hardness than the first metal layer. The forming the field plate includes forming a resist mask having an opening, the opening exposing a portion of the first insulating film overlapping the gate electrode, forming the first metal layer and the second metal layer in this order on an upper surface of the resist mask and inside the opening, and removing the resist mask and a portion of the first and second metal layers that are disposed on the resist mask by a lift-off process.

A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a group of negatively-charged ions. The gate electrode is located between the source and drain electrodes to define a drift region between the gate and drain electrodes. A group of negatively-charged ions are implanted into the drift region and over the 2DEG region and spaced apart from the gate and drain electrodes and spaced apart from an area directly beneath the gate and drain electrodes. The gate electrode is closer to the negatively-charged ions than the drain electrode, such that the negatively-charged ions deplete at least one portion of the 2DEG region which is near the gate electrode.

A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel opening, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel opening, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel opening prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel opening, the length of the gate structure can be advantageously decreased.

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

A transistor device includes a semiconductor substrate and a gate structure at the upper surface of the substrate. The gate structure is non-planar and includes a metal gate electrode with first and second sidewalls. A first dielectric layer is present over the gate structure. The first dielectric layer includes a first portion that overlies the first sidewall and a second portion that overlies the second sidewall. A portion of a conductive layer over the first dielectric layer forms a field plate with a first portion proximate to the second sidewall of the gate structure. A dielectric sidewall spacer on the first portion of the field plate is formed from a portion of a second dielectric layer, and the dielectric sidewall spacer does not contact the first dielectric layer.

An N-face polar GaN-based device, a composite substrate thereof, and a method of manufacturing the composite substrate are provided in the present disclosure. The N-face polar GaN-based composite substrate includes: a semiconductor substrate, an insulating layer on the semiconductor substrate and a GaN-based material layer on upper surface of the insulating layer; a surface of the GaN-based material layer attached to the insulating layer is Ga-face, and a surface of the GaN-based material layer away from the insulating layer is an N-face. In the present disclosure, the transfer technology is adopted to replace the direct epitaxial growth, which overcomes the difficult growth process, and the N-face polar GaN-based composite substrate with better quality can be obtained.