A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate. The high-potential-side region includes an n-type region and has a potential that is fixed at a power source voltage potential through a VB contact region in the n-type region. The high-potential-side region has a high-side driving circuit that drives an upper arm element of the inverter. An interphase region between adjacent high-potential-side regions has no GND contact region and no GND contact electrode arranged therein, and has only a p-type region at a ground potential constituting a low-potential-side region. The high-potential-side region of one phase has a p.sup.−-type opening between the high-side driving circuit of thereof and the high-side driving circuit or the GND contact region of an adjacent high-potential-side region that is of another phase and sandwiches the interphase region therebetween.

An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate. The high-potential-side region includes an n-type region and has a potential that is fixed at a power source voltage potential through a VB contact region in the n-type region. The high-potential-side region has a high-side driving circuit that drives an upper arm element of the inverter. An interphase region between adjacent high-potential-side regions has no GND contact region and no GND contact electrode arranged therein, and has only a p-type region at a ground potential constituting a low-potential-side region. The high-potential-side region of one phase has a p.sup.−-type opening between the high-side driving circuit of thereof and the high-side driving circuit or the GND contact region of an adjacent high-potential-side region that is of another phase and sandwiches the interphase region therebetween.

A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.