A semiconductor device includes: an n-doped drift region between first and second surfaces of a semiconductor body; a p-doped first region at the second surface; and an n-doped field stop region between the drift and first region. The field stop region includes first and second sub-regions with hydrogen related donors. A p-n junction separates the first region and first sub-region. A concentration of the hydrogen related donors, along a first vertical extent of the first sub-region, steadily increases from the pn-junction to a maximum value, and steadily decreases from the maximum value to a reference value at a first transition between the sub-regions. A second vertical extent of the second sub-region ends at a second transition to the drift region where the concentration of hydrogen related donors equals 10% of the reference value. A maximum concentration value in the second sub-region is at most 20% larger than the reference value.

A semiconductor device includes: a semiconductor chip including a first main surface on one side and a second main surface on the other side; a pn junction portion extending along the first main surface and formed inside the semiconductor chip; a trench configured to penetrate the pn junction portion from the first main surface and partition an element region in the semiconductor chip; an insulating film configured to cover a side wall and a bottom wall of the trench; and an embedded electrode embedded in the trench via the insulating film, wherein the bottom wall of the trench includes a protrusion protruding from a lower end of the insulating film toward an inner upper side of the insulating film in a depth direction of the trench.

A power device and a guard ring structure surrounding the power device are provided. The power device includes: a buried layer of a first conductivity type and a buried layer of a second conductivity type disposed within a substrate; a body region of the first conductivity type and a drift region of the second conductivity type disposed on the buried layer of the first conductivity type; and a gate electrode, a source electrode, and a drain electrode disposed on the body region of the first conductivity type and the drift region of the second conductivity type. The guard ring structure includes: a first guard ring of the second conductivity type adjacent to the power device; a second guard ring of the first conductivity type adjacent to the first guard ring; and a third guard ring of the second conductivity type adjacent to the second guard ring.

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.

A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.

A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction.

The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.