A semiconductor device is proposed. The semiconductor device includes a semiconductor body including a first main surface. A plurality of trench electrode structures extend in parallel along a first lateral direction. A first one of the plurality of trench electrode structures includes a gate electrode. A gate contact is electrically connected to the gate electrode in a gate contact area. The gate contact area is arranged in a first section along the first lateral direction. An isolation structure is arranged between the gate contact and the semiconductor body in the gate contact area. A bottom side of the isolation structure is arranged between a bottom side of the first one of the plurality of trench electrode structures and the first main surface along a vertical direction. The gate contact extends up to or below the first main surface along the vertical direction.

An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

An integrated circuit according to some example embodiments of inventive concepts includes a substrate including a well including dopants of a first conductivity type, a first device region on the well, the first device region extending in a first direction parallel to the substrate, and a first isolation element inside the well, the first isolation element extending in the first direction. The first isolation element includes a first power rail configured to receive a power source voltage, and a first doping region between the first power rail and the well, the first doping region configured to transfer the power source voltage from the first power rail to the well, and including dopants of the first conductivity type.

An integrated circuit according to some example embodiments of inventive concepts includes a substrate including a well including dopants of a first conductivity type, a first device region on the well, the first device region extending in a first direction parallel to the substrate, and a first isolation element inside the well, the first isolation element extending in the first direction. The first isolation element includes a first power rail configured to receive a power source voltage, and a first doping region between the first power rail and the well, the first doping region configured to transfer the power source voltage from the first power rail to the well, and including dopants of the first conductivity type.

A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.

A semiconductor device includes a semiconductor base body, and a first main electrode and a second main electrode provided on the semiconductor base body. The semiconductor base body includes a drift region of a first conductivity type through which a main current flows, a column region of a second conductivity type arranged adjacent to the drift region in parallel to a current passage of the main current, a second electrode-connection region of the first conductivity type electrically connected to the second main electrode, and a low-density electric-field relaxation region of the first conductivity type having a lower impurity concentration than the drift region and arranged between the second electrode-connection region and the column region.

A semiconductor device includes a semiconductor base body, and a first main electrode and a second main electrode provided on the semiconductor base body. The semiconductor base body includes a drift region of a first conductivity type through which a main current flows, a column region of a second conductivity type arranged adjacent to the drift region in parallel to a current passage of the main current, a second electrode-connection region of the first conductivity type electrically connected to the second main electrode, and a low-density electric-field relaxation region of the first conductivity type having a lower impurity concentration than the drift region and arranged between the second electrode-connection region and the column region.