A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.

A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si.sub.1-xGe.sub.x, Si.sub.1-xC.sub.x, Si.sub.1-x-yGe.sub.xSn.sub.y, Si.sub.1-x-y-zGe.sub.xSn.sub.yC.sub.z, Ge.sub.1-xSn.sub.x, group IIIA-nitrides, semiconductor oxides, and any combination thereof.