A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate as a depth of the first trench is greater than a depth of the second trench; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.

A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

A method of fabricating an IC includes forming a layer stack thereon including silicon nitride layer on a first silicon oxide layer, with a second silicon oxide layer thereon on a substrate including a semiconductor material. The layer stack is etched to form ≥1 trench that is at least 2 microns deep into the semiconductor material. A dielectric liner is formed on sidewalls and a bottom of the trench. A polysilicon layer is formed on the dielectric liner that fills the trench and extends lateral to the trench. Chemical mechanical planarization (CMP) processing stops on the silicon nitride layer to remove the polysilicon layer and the second silicon oxide layer to form a trench structure having a polysilicon fill. After the CMP processing, thermal oxidation oxidizes exposed regions of the polysilicon layer to form a polysilicon oxide layer. After the thermal oxidizing, the silicon nitride layer is removed.