Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.