A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.

A semiconductor device according to the present invention includes a semiconductor substrate including at least a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type provided in the upper layer of the third semiconductor layer; a first gate trench extending in the thickness direction through the fourth, third, and second semiconductor layers to the inside of the first semiconductor layer; an interlayer insulating film; a first main electrode provided in contact with the fourth semiconductor layer; and a second main electrode provided on the side opposite the first main electrode. The first gate trench includes a first gate electrode on the lower side and a second gate electrode on the upper side.

A semiconductor device according to the present invention includes a semiconductor substrate including at least a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type provided in the upper layer of the third semiconductor layer; a first gate trench extending in the thickness direction through the fourth, third, and second semiconductor layers to the inside of the first semiconductor layer; an interlayer insulating film; a first main electrode provided in contact with the fourth semiconductor layer; and a second main electrode provided on the side opposite the first main electrode. The first gate trench includes a first gate electrode on the lower side and a second gate electrode on the upper side.

A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.

Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.

The present application provides an SGT MOSFET device, a gate structure of which is a left-right structure, wherein a second field plate conductive material layer with a depth greater than that of a gate conductive material layer is formed between a source conductive material layer and the gate conductive material layer. When the device is reversely biased, depletion capability with respect to the drift region at a side close to a channel region is enhanced due to the feature that a spacing between the second field plate conductive material layer and the drift region is less than a spacing between the source conductive material layer and the drift region. The present application further provides a method for manufacturing an SGT MOSFET device.