A semiconductor device includes a semiconductor layer, a source electrode and a drain electrode that are disposed on the upper surface of the semiconductor layer, a gate electrode disposed on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film disposed on the gate electrode, and a field plate disposed on the first insulating film, at least part of the field plate overlapping the gate electrode, the field plate including a first metal layer and a second metal layer disposed on the upper surface of the first metal layer, the first metal layer containing gold, the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium.

A semiconductor device includes a semiconductor layer, a source electrode and a drain electrode that are disposed on the upper surface of the semiconductor layer, a gate electrode disposed on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film disposed on the gate electrode, and a field plate disposed on the first insulating film, at least part of the field plate overlapping the gate electrode, the field plate including a first metal layer and a second metal layer disposed on the upper surface of the first metal layer, the first metal layer containing gold, the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.

A semiconductor device, allowing easy hole extraction, including a semiconductor substrate having drift and base regions; and transistor and diode portions, in which trench portions and mesa portions are formed, is provided. The transistor portion includes emitter and contact regions above the base region and exposed to an upper surface of the semiconductor substrate. The emitter region has a higher concentration than the drift region. The contact region has a higher concentration than the base region. The mesa portions include boundary mesa portion(s) at a boundary between the transistor and diode portions. The trench portions include dummy trench portion(s) provided adjacent to a trench portion adjacent to the boundary mesa portion(s) and provided on the transistor portion side relative to the trench portion adjacent to the boundary mesa portion(s). The boundary mesa portion(s) include a base boundary mesa portion in which the base region is exposed to the upper surface.

A semiconductor device, allowing easy hole extraction, including a semiconductor substrate having drift and base regions; and transistor and diode portions, in which trench portions and mesa portions are formed, is provided. The transistor portion includes emitter and contact regions above the base region and exposed to an upper surface of the semiconductor substrate. The emitter region has a higher concentration than the drift region. The contact region has a higher concentration than the base region. The mesa portions include boundary mesa portion(s) at a boundary between the transistor and diode portions. The trench portions include dummy trench portion(s) provided adjacent to a trench portion adjacent to the boundary mesa portion(s) and provided on the transistor portion side relative to the trench portion adjacent to the boundary mesa portion(s). The boundary mesa portion(s) include a base boundary mesa portion in which the base region is exposed to the upper surface.

A method for manufacturing a laterally diffused metal oxide semiconductor device and a semiconductor device are provided. A body region is formed before forming a gate dielectric layer and a gate conductor, thereby reducing a channel length of the semiconductor device, thus reducing the on-resistance. In addition, a drift region serves as both a region withstanding a high voltage and a diffusion suppression region for suppressing lateral diffusion of the body region, thereby further reducing the channel length of the semiconductor device, thus manufacturing a short-channel semiconductor device.

A method for manufacturing a laterally diffused metal oxide semiconductor device and a semiconductor device are provided. A body region is formed before forming a gate dielectric layer and a gate conductor, thereby reducing a channel length of the semiconductor device, thus reducing the on-resistance. In addition, a drift region serves as both a region withstanding a high voltage and a diffusion suppression region for suppressing lateral diffusion of the body region, thereby further reducing the channel length of the semiconductor device, thus manufacturing a short-channel semiconductor device.

A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.

A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.