A resin membrane (8) covering a semiconductor device (5) and a dicing line (7) of a semiconductor substrate (1) is formed on a main surface of the semiconductor substrate (1). The resin membrane (8) around the first electrode (2) is removed and the resin membrane (8) on the second electrode (3,4) is removed to form a first contact hole (9) without removing the resin membrane (8) on the dicing line (7). A resin film (11) is applied to a top surface of the resin membrane (8) to form a hollow structure (12) around the first electrode (2). The resin film (11) is patterned to form a second contact hole (13) connected to the first contact hole (9) and a first opening (14) above the dicing line (7) simultaneously. After forming the first opening (14), the semiconductor substrate (1) is diced along the dicing line (7).

In one embodiment, a semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, and is formed of a second insulating material different from the first insulating material.

A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

A method of manufacturing a semiconductor device includes receiving film thickness distribution data of a polished first insulating film of a substrate; calculating processing data for reducing a difference between a film thickness at a center side of the substrate and a film thickness at a periphery side of the substrate, based on the film thickness distribution data; loading the substrate into a process chamber; supplying a process gas to the substrate; and correcting a film thickness of the first insulating film based on the processing data by activating the process gas so that a concentration of active species of the process gas generated at the center side of the substrate differs from a concentration of active species of the process gas generated at the periphery side of the substrate.

In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.

A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer (203) on an upper surface of a device (S1); implanting silicon ions and/or indium ions in a region of the first dielectric layer (203) corresponding to an ohmic contact electrode region, and in the ohmic contact electrode region of the device (S2); growing a second dielectric layer (206) on an upper surface of the first dielectric layer (203) (S3); activating the silicon ions and/or the indium ions by means of a high temperature annealing process, so as to form an N-type heavy doping (S4); respectively removing portions, corresponding to the ohmic contact electrode region, of the first dielectric layer (203) and the second dielectric layer (206) (S5); growing a metal layer (208) on the upper surface of the ohmic contact electrode region of the device, so as to form an ohmic contact electrode (S6). The ohmic contact electrode prepared by the method can ensure that the metal layer (208) has flat surfaces, smooth and regular edges, and said electrode has stable device breakdown voltage, and is reliable and has a long service life.

A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.