A semiconductor device includes a substrate that includes an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode on the channel pattern, an active contact electrically connected to the source/drain pattern, and a gate contact electrically connected to the gate electrode. The active contact includes a first barrier pattern, a first seed pattern on the first barrier pattern, a first fill pattern on the first seed pattern, and a first metal-containing pattern between the first seed pattern and the first fill pattern. The first metal-containing pattern includes tungsten nitride. A nitrogen concentration of the first metal-containing pattern decreases in a direction toward the substrate.

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and between the first and second source-drain regions. Also included are a front side wiring network, having a plurality of front side wires, on a front side of the field effect transistor; a front side conductive path electrically interconnecting one of the front side wires with the first source-drain region; a back side power rail, on a back side of the FET; and a back side contact electrically interconnecting the back side power rail with the second source-drain region. A dielectric liner and back side dielectric fill are on a back side of the gate adjacent the back side contact, and they electrically confine the back side contact in a cross-gate direction.

An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.

A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.