An etching method includes: preparing a substrate including a first region containing silicon and nitrogen, and a second region containing silicon and oxygen; and etching the second region while firming a tungsten-containing protective layer on the first region, by exposing the first and second regions to plasma generated from a processing gas containing carbon, fluorine, and tungsten.

Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity and low-photosensitivity photoresist are applied to a substrate and exposed at the same time with use of a dual-tone mask. After being developed, one photoresist forms an overhang over a sheltered region. The mold formed by the photoresists is filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the sheltered region forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

A semiconductor structure includes an isolation feature disposed over a semiconductor substrate, a semiconductor fin disposed over the semiconductor substrate and adjacent to the isolation feature, a source/drain (S/D) feature disposed over the semiconductor substrate and apart from the isolation feature, an interlayer dielectric (ILD) layer disposed over the isolation feature and the S/D feature, a first contact plug disposed in the ILD layer and over the isolation feature, a second contact plug disposed in the ILD layer and over the S/D feature, and a dielectric layer between surfaces of the first contact plug and the ILD layer and between a sidewall of the second contact plug and the ILD layer, where a bottom surface of the second contact plug is free of the dielectric layer.

A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.