A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.

A Through-Silicon Via (TSV) product, a TSV sample, and a method for manufacturing the same are provided. The method includes operations as follows. A first metal layer is deposited on a bottom of each of TSVs, the first metal layer covering the bottom of the TSV. Pre-prepared adhesive is filled on an inner wall in a middle of each of TSVs of a to-be-processed sample. A second metal layer is deposited on a top of each of the TSVs, the second metal layer covering on the top of an opening of the TSV. A capping layer is deposited on the second metal layer, to obtain a preprocessed to-be-processed sample. The preprocessed to-be-processed sample is cut in a preset cutting manner by using a dual-beam Plasma Focused Ion Beam (PFIB), to form a TSV sample with a cross-section of each of the TSVs is exposed.

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T.sub.1 at a first end of the opening, and a thickness T.sub.2 at a second end of the opening, and R.sub.1 is a ratio of T.sub.1 to T.sub.2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T.sub.3 at the first end of the opening, a thickness T.sub.4 at the second end of the opening, R.sub.2 is a ratio of T.sub.3 to T.sub.4, and R.sub.1 is greater than R.sub.2.

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

A flexible three-dimensional electronic device includes a polymer layer having a first side and a second side that is opposite of the first side. A first flexible substrate carrying a first electronic component is arranged on the first side of the polymer layer. A second flexible substrate carries a second electronic component. The second flexible substrate is a flexible silicon substrate arranged on the second side of the polymer layer. An electrically conductive via passes through the polymer layer to electrically connect the first and second electronic components.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer, wherein an upper surface of the first wafer includes a first bonding pad configured to connect to a first signal; fabricating a first redistribution layer (RDL) on the first wafer, comprising a first wiring electrically connected to the first bonding pad, and the first wiring includes a first landing pad; bonding a second wafer on the first RDL, wherein the second wafer includes a second bonding pad configured to connect the first signal and located corresponding to the first bonding pad; fabricating a first through silicon via (TSV) with a bottom connected to the first landing pad at a position corresponding to the first landing pad; and fabricating a second RDL on the second wafer to connect the second bonding pad and the first TSV. This wafer stacking method improves the manufacturing yield.

An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

Embodiments described herein may be related to apparatuses, processes, and techniques related to well biasing using a buried power rail (BPR) within a circuit structure. Embodiments include using a silicide material between the BPR and a well, where the silicide material provides ohmic contact between the BPR and the well. Other embodiments may be described and/or claimed.

In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.