An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.

A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 μm. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

A method of electroplating metal into features of a partially fabricated electronic device on a substrate having high open area portions is provided. The method includes initiating a bulk electrofill phase with a pulse at a high level of current; reducing the current to a baseline current level; and optionally increasing the current in one or more steps until electroplating is complete.

A process for manufacturing electroacoustic modules including: forming an assembly with a redistribution structure and a plurality of dice arranged in a dielectric region; forming a wafer with a semiconductor body and a plurality of respective unit portions laterally staggered, each of which includes a respective supporting region, set in contact with the semiconductor body, and a number of actuators; reducing the thickness of the semiconductor body and then selectively removing portions of the semiconductor body so as to singulate, starting from the wafer, a plurality of transduction structures, each including a semiconductor substrate, which contacts a corresponding supporting region and is traversed by cavities delimited by portions of the supporting region that form membranes mechanically coupled to the actuators; and then coupling the transduction structures to the redistribution structure of the assembly.

The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.