A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a fissure. A single pulsed radiation beam is split into a first pulsed radiation beam for cutting at least one of the trenches and a second pulsed radiation beam for cutting the fissure. When cutting a fissure on the wafer in a cutting direction along a cutting street, the first and second radiation beams are directed simultaneously with the first radiation beam leading and the second radiation beam trailing. For cutting a fissure in the opposite cutting direction, a third pulsed radiation beam for trenching is split from said single pulsed radiation beam.

A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.

A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

The present disclosure provides a thin film transistor array substrate, a method for manufacturing the same and a display device. The method includes forming, on a substrate, a gate electrode, a common electrode, a gate insulation layer, an active layer and a source-drain metal layer, and forming, on the resultant substrate, a pixel electrode and a passivation layer by one patterning process.

Disclosed herein is a technique for providing a layout structure for a semiconductor integrated circuit with SOI transistors with an antenna error that could occur in a buried insulator under a source or drain taken into account. A standard cell, which is at least one of a plurality of standard cells that form the semiconductor integrated circuit, includes a signal interconnect serving as an output node to output a signal to outside of the standard cell, and an antenna diode formed between the signal interconnect and a substrate or a

Disclosed herein is a technique for providing a layout structure for a semiconductor integrated circuit with SOI transistors with an antenna error that could occur in a buried insulator under a source or drain taken into account. A standard cell, which is at least one of a plurality of standard cells that form the semiconductor integrated circuit, includes a signal interconnect serving as an output node to output a signal to outside of the standard cell, and an antenna diode formed between the signal interconnect and a substrate or a