The invention relates to an arrangement for a power converter (12) comprising at least one power module (1) comprising power semiconductor components (5) and a cooler (10), wherein the cooler (10) has a curved surface and the power module (1) is arranged on the surface and is connected in a positive fit to the cooler (10). The invention also relates to an associated manufacturing method as well as to a power converter with said type of arrangement and to a vehicle with a power converter.

The invention relates to an arrangement for a power converter (12) comprising at least one power module (1) comprising power semiconductor components (5) and a cooler (10), wherein the cooler (10) has a curved surface and the power module (1) is arranged on the surface and is connected in a positive fit to the cooler (10). The invention also relates to an associated manufacturing method as well as to a power converter with said type of arrangement and to a vehicle with a power converter.

A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

In a semiconductor device, a semiconductor element has a front electrode and a back electrode. The back electrode is connected to a wiring member through a bonding member. Wire pieces are disposed in the bonding member, and bonded to a bonding surface of the wiring member to protrude toward the semiconductor element. The bonding member has, in a plan view, a central region that overlaps with a central portion of the semiconductor element including an element center, and an outer peripheral region that includes a portion overlapping with an outer peripheral portion of the semiconductor element surrounding the central portion and surrounds the central region. At least four wire pieces are disposed in the outer peripheral region at positions corresponding to at least four respective corners of the semiconductor element. At least one wire piece is disposed to extend toward the element center in the plan view.

A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.

Provided is a semiconductor package in which a bonding structure is formed using metal grains included in metal powder layers having a coefficient of thermal expansion (CTE) similar with those of a substrate and a conductor so as to minimize generation of cracks and to improve reliability of bonded parts.

A planar power module includes a second substrate arranged parallel to a first substrate, with the substrates respectively having a dielectric layer interposed between two conductive layers, such that one of the conductive layers of each substrate together forms parallel external conductive surfaces of the power module. The power module includes direct current (DC) bus bars, alternating current (AC) bus bars, and semiconductor switching dies arranged between the substrates. The dies are electrically connected to the bus bars, with each respective die electrically connected to a conductive layers of the first or second substrates. A polymer molding material partially surrounds the substrates and the switching dies. An electric powertrain system includes an electric machine, a propulsion battery pack, and a traction power inverter module (TPIM) having the power module. The power module is a three-phase full-bridge inverter circuit. An electric powertrain and motor vehicle use the power module.

A semiconductor device package and manufacturing method thereof are provided. The semiconductor device package includes a first conductive structure, a second conductive structure, a connection element, a conductive member, an encapsulant and a binding layer. The first conductive structure includes a first circuit layer. The second conductive structure is disposed over the first conductive structure. The connection element is disposed on and electrically connected to the first circuit layer. The conductive member protrudes from the second conductive structure. The encapsulant is disposed between the first conductive structure and the second conductive structure. The binding layer is disposed between the second conductive structure and the encapsulant.

Provided is a semiconductor device including: a laminated substrate in which a circuit layer, an insulating layer, and a metal layer are sequentially laminated. A slit is formed in the circuit layer. A recess recessed from one surface side facing the insulating layer toward the other surface side is formed in the metal layer. The recess of the metal layer has a relaxation portion at least partially overlapping the slit of the circuit layer in a planar view.

According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion.