A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

The assembly of bus bars according to the invention comprises a plurality of sectors of bus bars (S1 to S6) which are arranged, in a connected manner and with electrical contact, around a central axis (C) and upper and lower closing plates (BPD) which are perpendicular to the central axis, the sectors of bus bars each comprising an external portion of bus bar (B11 to B16) and at least one internal portion of bus bar (B21 to B26, B31 to B36) which delimit a plurality of internal volumes, the upper and lower closing plates being in contact against upper and lower faces of the portions of bus bar, respectively, and the portions of bus bar comprising a plurality of electrical contact faces of the type referred to as “press pack”.

According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface.

A semiconductor device includes: a first semiconductor chip including a junction-type FET; a second semiconductor chip including a MOSFET; and a junction-type FET adjustment resistor disposed between a gate electrode of the junction-type FET and a source electrode of the MOSFET. The junction type FET and the MOSFET are cascode-connected. The junction-type FET adjustment resistor includes a first resistance circuit for a switching on operation and a second resistance circuit for a switching off operation.

Provided is a technique for preventing warps of cooling plates due to a contraction of a joining material, thereby preventing a reduction in cooling performance of a semiconductor device. The semiconductor device includes the following: a first cooling plate; a second cooling plate facing the first cooling plate; a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and a case containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip. The semiconductor chip is mounted in a semiconductor-chip mounting part between the first cooling plate and the second cooling plate. The case is provided with a portion corresponding to the semiconductor-chip mounting part and to surroundings thereof. The portion has an up-and-down width greater than an up-and-down width of the remaining portions of the case.

Provided is a technique for preventing warps of cooling plates due to a contraction of a joining material, thereby preventing a reduction in cooling performance of a semiconductor device. The semiconductor device includes the following: a first cooling plate; a second cooling plate facing the first cooling plate; a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and a case containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip. The semiconductor chip is mounted in a semiconductor-chip mounting part between the first cooling plate and the second cooling plate. The case is provided with a portion corresponding to the semiconductor-chip mounting part and to surroundings thereof. The portion has an up-and-down width greater than an up-and-down width of the remaining portions of the case.

A dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate.

In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.