A semiconductor module has at least two semiconductor components which are arranged within a housing in each case between two electrical conduction elements and are electrically conductively connected to the electrical conduction elements. The electrical conduction elements respectively have a contact extension that is led out of the housing, wherein two contact extensions arranged in different planes are connected to one another outside the housing via a contact element, which forms a current path between the two contact extensions outside the housing.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

A semiconductor device includes: a first semiconductor chip having a metal layer on a top surface; a first wiring member arranged to face the metal layer; a sintered-metal layer arranged between the metal layer and the first wiring member, having a first region and a plurality of second regions provided inside the first region, the second regions having lower tensile strength than the first region; and a metallic member arranged inside the sintered-metal layer, wherein the second regions of the sintered-metal layer have lower tensile strength than the metal layer of the first semiconductor chip.

A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.

A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.

A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.

A multiphase inverter apparatus includes an insulating substrate, a plurality of half bridge circuits and a phase output lead for each half bridge circuit. The substrate includes a conductive redistribution structure on a first surface and having at least one low voltage bus and at least one high voltage bus. Each half-bridge circuit is electrically coupled between a low voltage bus and a high voltage bus and includes: a packaged low side switch; a packaged high side switch; and a phase output electrically coupled with the respective phase output lead. The packaged low side and high side switches are arranged on the first surface of the substrate. The phase output lead is arranged on and electrically coupled to the packaged low side and high side switches such that the low side and high side switches are arranged vertically between the phase output lead and the first surface of the substrate.

A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.