A resin composition is disclosed that includes a thermosetting base resin; a curing agent; an inorganic filler; and at least one fluorine resin powder selected from polyvinylidene fluoride, polychlorotetrafluoroethylene, and a tetrafluoroethylene/perfluoro(alkyl vinyl ether)/chlorotrifluoroethylene copolymer, and a semiconductor device which is fabricated by being sealed using a sealant formed of the resin composition.

Provided herein is a conductive coating material that can be spray coated to form a shielding layer having desirable shielding performance, and desirable adhesion to a package. A shielded package producing method using the conductive coating material is also provided. The conductive coating material comprises at least (A) 100 parts by mass of a binder component containing 5 to 30 parts by mass of a solid epoxy resin that is solid at ordinary temperature, and 20 to 90 parts by mass of a liquid epoxy resin that is liquid at ordinary temperature, (B) 200 to 1800 parts by mass of metallic particles, and (C) 0.3 to 40 parts by mass of a curing agent. The conductive coating material has a viscosity of 3 to 30 dPa.Math.s.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

A liquid sealing material which has excellent PCT (pressure cooker test) resistance, and an electronic component which is obtained by sealing a part to be sealed with use of the liquid sealing material. A liquid sealing material contains (A) a liquid epoxy resin, (B) a curing agent, (C) a silica filler and (D) a coupling agent, and the boron content in the silica filler (C) has an average of 1-50 ppm.

A resin composition including an epoxy resin monomer, a novolac resin including a compound having a structural unit represented by Formula (I), and a filler; in which the filler has at least 4 peaks in a particle size distribution measured by laser diffractometry, in which four of the peaks are present respectively in ranges of not less than 0.01 μm and less than 1 μm, not less than 1 μm and less than 10 μm, from 10 μm to 50 μm, and from 20 μm to 100 μm, and in which a peak present in a range of from 10 μm to 50 μm includes an aluminum oxide particle, and a peak present in a range of from 20 μm to 100 μm includes a boron nitride particle. In Formula (I) each of R.sup.1, R.sup.2 and R.sup.3 independently represents a hydrogen atom, an alkyl group, or the like. m represents 0 to 2, and n represents 1 to 7. ##STR00001##

A semiconductor-chip-encapsulating resin composition according to the present disclosure contains: an epoxy resin; a curing agent; and a low-valent titanium oxide, of which a titanium atom has an oxidation number less than +IV. A semiconductor package according to the present disclosure includes: a semiconductor chip; and an encapsulation resin which covers the semiconductor chip and which is a cured product of the semiconductor-chip-encapsulating resin composition.

Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure is provided on a substrate to dissipates heat of the substrate to outside, and includes: a water-based coating material layer provided on the substrate and including a water-based coating material, and fillers having an average particle size of 30 μm to 150 μm; and a resin layer provided on the water-based coating material layer and containing a thermosetting resin. The fillers have a far-infrared emissivity of 0.8 or more, and an average aspect ratio of 1 to 12 as measured as a ratio of lengths along the long axis and the short axis through the center of gravity of the fillers. At least 80% of the total number of fillers has a length that is at least 1.7 times longer than the total thickness of the water-based coating material of the water-based coating material layer and the thermosetting resin of the resin layer, as measured along the long axis through the center of gravity of the fillers.

Embodiments of the disclosure provide a package structure and method of forming the same. The package structure includes a first die, a first encapsulant, a first RDL structure, a die stack structure and a second encapsulant. The first encapsulant laterally encapsulates the first die. The first RDL structure is electrically connected to the first die, and disposed on a first side of the first die and the first encapsulant. The die stack structure is electrically connected to the first die and disposed on a second side of the first die opposite to the first side. The second encapsulant is located over the first encapsulant and laterally encapsulating the die stack structure. A sidewall of the first encapsulant is aligned with a sidewall of the second encapsulant.

A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board.