A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.

A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

An addition-curable silicone resin composition which exhibits good adhesion to a substrate and has good compatibility with an inorganic filler, as well as a cured product thereof and a highly reliable semiconductor device encapsulated with the cured product, are provided. The addition-curable silicone resin composition includes (A) a linear or branched organopolysiloxane having at least one alkenyl group, said organopolysiloxane comprising at least one unit selected from R.sup.1R.sup.2SiO.sub.2/2 and R.sup.1R.sup.2.sub.2SiO.sub.1/2 units, and at least one unit selected from R.sup.2′.sub.2SiO.sub.2/2, R.sup.2′.sub.3SiO.sub.1/2 and R.sup.2′SiO.sub.3/2 units, wherein a percentage of a total number of the R.sup.1R.sup.2SiO.sub.2/2 and R.sup.1R.sup.2.sub.2SiO.sub.1/2 units, relative to a total number of all siloxane units, is from 0.001% to 50%, and wherein R.sup.1 is, independently at each occurrence, a hydroxy group or an alkoxy group of 1 to 30 carbon atoms; R.sup.2 is, independently at each occurrence, a group selected from a substituted or unsubstituted saturated hydrocarbon group of 1 to 12 carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group of 6 to 12 carbon atoms, an alkenyl group of 2 to 10 carbon atoms, and the groups as defined for R.sup.1; and R.sup.2′ is a groups selected from the groups as defined for R.sup.2 other than those as defined for R.sup.1, with the proviso that at least one of R.sup.2 and R.sup.2′ is an alkenyl group; (B) an organohydrogenpolysiloxane having at least two hydrosilyl groups, in an amount such that the ratio of the number of hydrosilyl groups in component (B) to a total number of alkenyl groups in component (A) is from 0.1 to 4; and (C) a catalytic amount of a hydrosilylation catalyst.

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

A curing agent composition is capable of curing a base resin containing a 2-methylene-1,3-dicarbonyl compound. The curing agent composition contains a specific 2-methylene-1,3-dicarbonyl compound and an initiator. A two-part mixing adhesive contains the curing agent composition and a base resin containing another specific 2-methylene-1,3-dicarbonyl compound.

A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.

Provided is an encapsulating resin composition for a power device including an epoxy resin, an inorganic filler, a curing agent, and a curing accelerator. This composition is molded under a condition of 175° C. for 2 minutes and then subjected to after-curing under a condition of 175° C. for 4 hours to obtain a test piece having a diameter of 100 mm and a thickness of 2 mm, and a half width of a current-time curve obtained by measuring the test piece with a thermally stimulated depolarization current method according to an order of (i) to (v) below is equal to or less than 800 seconds, (i) increase a temperature of the test piece to 150° C. at a rate of 5° C./min without applying a voltage, (ii) applying a constant voltage of 500 V for 30 minutes while maintaining the temperature of the test piece at 150° C., (iii) lower the temperature of the test piece to 45° C. at a rate of 5° C./min while applying the constant voltage of 500 V, (iv) stop applying the voltage while maintaining the temperature of the test piece at 45° C. and leave the test piece to stand for 5 minutes, and (v) increase the temperature of the test piece at a rate of 3.5° C./min without applying a voltage to the test piece, and measure a value of a current flowing during the increase in the temperature to obtain a current-time curve.

A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.