H01L23/295

SEMICONDUCTOR PACKAGE INCLUDING AN ENCAPSULANT
20230083493 · 2023-03-16 ·

A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantially equal to or smaller than that of the first step.

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.

Adhesive bonding composition and electronic components prepared from the same

A curable resin or adhesive composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and at least one energy converting material, preferably a phosphor, capable of producing light when exposed to radiation (typically X-rays). The material is particularly suitable for bonding components at ambient temperature in situations where the bond joint is not accessible to an external light source. An associated method includes: placing a polymerizable adhesive composition, including a photoinitiator and energy converting material, such as a down-converting phosphor, in contact with at least two components to be bonded to form an assembly; and, irradiating the assembly with radiation at a first wavelength, capable of conversion (down-conversion by the phosphor) to a second wavelength capable of activating the photoinitiator, to prepare items such as inkjet cartridges, wafer-to-wafer assemblies, semiconductors, integrated circuits, and the like.

Manufacturing method of integrated circuit packaging structure

A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.

Resin composition
11634615 · 2023-04-25 · ·

A resin composition contains one or more 2-methylene-1,3-dicarbonyl compounds. At least one of the one or more 2-methylene-1,3-dicarbonyl compounds has a molecular weight of 220 to 10,000, and the amount by weight of those of the 2-methylene-1,3-dicarbonyl compounds having a molecular weight of less than 220 relative the entire resin composition of 1 is 0.00 to 0.05. The 2-methylene-1,3-dicarbonyl compounds contain a structural unit represented by formula (I) below. ##STR00001##

Method of Manufacturing an Integrated Fan-out Package having Fan-Out Redistribution Layer (RDL) to Accommodate Electrical Connectors
20230123427 · 2023-04-20 ·

A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

Method for Manufacturing Semiconductor Package with Connection Structures Including Via Groups
20230122816 · 2023-04-20 ·

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR

A power module includes an insulating substrate, a heat dissipation member, and an electrode plate. An IGBT and a diode are mounted on the insulating substrate. The heat dissipation member is bonded to the insulating substrate by first solder. The electrode plate is disposed so as to overlap at least a part of the semiconductor element. The main surface of the insulating substrate is curved so as to have a shape convex toward the heat dissipation member. The first solder is thicker at the edges than at the center in a plan view. The semiconductor element is bonded to the electrode plate by second solder.

RESIN SHEET

A resin sheet is made using a resin composition containing a thermosetting component (A). The thermosetting component (A) contains a maleimide resin. A thermal diffusion rate of the thermally cured resin sheet is 1.0 × 10.sup.-6 m.sup.2/s or more. The resin sheet has a thickness in a range from 5 .Math.m to 120 .Math.m .

SEMICONDUCTOR PACKAGES AND METHODS FOR MANUFACTURING THEREOF

Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.