An encapsulant sheet suitable for encapsulating a light-emitting element in a self-luminous display, etc. A resin sheet having a polyolefin as a base resin, wherein the resin sheet is created as an encapsulant sheet for a self-luminous display or for a direct backlight, the melt viscosity of the encapsulant sheet, at a shear velocity of 2.43×10 sec.sup.−1 and measured at a temperature of 120° C., being 5.0×10.sup.3 poise to 1.0×10.sup.5 poise inclusive.

Provided is a hot-melt curable silicone composition that forms a cured product that can be cured at a temperature of 100° C. or lower, has excellent storage stability, is relatively hard from curing, and has low surface tack, and a sheet or film formed from the same. The curable silicone composition comprises: (A) a solid organopolysiloxane resin that contains at a mass ratio of 0:100 to 90:10 (Al) an organopolysiloxane resin having a curing reactive functional group and containing 20 mol % or more of a Q unit (i.e., a SiO.sub.4/2 unit), and (A2) an organopolysiloxane resin not having a curing reactive functional group and containing 20 mol % or more of a Q unit; (B) 10 to 100 parts by mass of a straight-chain or branched branched chain organopolysiloxane having a curing reactive functional group and is liquid or has plasticity; (C) an organohydrogenpolysiloxane; and (D) a photoactivated hydrosilylation reaction catalyst.

In order to carry out the encapsulation of electronic components, the invention proposes to cover the electronic components (7) with a heat-polymerisable material corresponding to a composition comprising a diimide constituent and a diamine constituent, in which the diimide constituent has been predissolved in the diamine constituent, and to heat the assembly obtained under conditions suitable for carrying out the curing of the material by an addition polymerisation reaction between said diimide constituent and the diamine constituent. The invention finds an application in particular in the field of electronic power modules.

6

A silicone resin liquid composition containing a silicone resin is provided. The .sup.29Si-NMR measurement of the resin exhibits a ratio of the area of signals assigned to A3 silicon atoms to the area of all signals derived from silicon atoms of 51% to 69%. An A3 silicon atom represents a silicon atom to which are bonded three oxygen atoms bonded to another silicon atom.

In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.

An encapsulant sheet suitable for encapsulating a light-emitting element in, for example, a self-luminous display or for direct backlights. The encapsulant sheet is a single-layer or multi-layer resin sheet that includes an adhesive layer exposed at a topmost surface. The Vicat softening point is greater than 60° C. and no higher than 100° C. The melt viscosity of the encapsulant sheet, at a shear velocity of 2.43×10 sec.sup.−1 and measured at a temperature of 120° C. is at least 5.0×10.sup.4 poise and no more than 1.0×10.sup.5 poise. The adhesive layer contains a polyolefin and a silane component, and a content of the silane component relative to the resin component of the adhesive layer is at least 0.03% by mass and less than 10% by mass.

An integrated silicone for protecting electronic devices includes a base resin, a thermal initiator, and a photoinitiator.

A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.