A semiconductor package includes a substrate, an electronic component mounted on an upper surface of the substrate so that a lower surface of the electronic component faces the upper surface of the substrate, a heat slug disposed on an upper surface of the electronic component so that a lower surface of the heat slug faces the upper surface of the electronic component, a bonding material bonding the heat slug to the upper surface of the electronic component, and an encapsulant in which the heat slug and the electronic component are embedded. A side surface of the heat slug extending between an edge of the lower surface of the heat slug and an edge of an upper surface of the heat slug forms a recess with the upper surface of the electronic component.

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a top surface. A conductive pad is over the top surface. An upper passivation layer is over the top surface and the conductive pad and includes a first implanted region. A polymer layer is over the upper passivation layer and the conductive pad. A conductive via penetrates through the upper passivation layer and the polymer layer, and electrically coupled to the conductive pad. A method for manufacturing a semiconductor structure is also provided.

A method of manufacturing an electronic component module includes a sacrificial-body arrangement step of disposing a sacrificial body on a first principal surface of a support, the support including the first principal surface and a second principal surface, the sacrificial body being smaller than the first principal surface when viewed in a thickness direction of the support, a resin molding step of molding a resin structure on the first principal surface so as to cover the sacrificial body disposed on the first principal surface, a recess forming step of forming a recess in the resin structure by removing the sacrificial body, a wiring-layer forming step of forming a wiring layer on a side surface of the recess and on a principal surface of the resin structure, the principal surface connecting with the side surface, and a component mounting step of mounting an electronic component in the recess.

A high-frequency module includes a semiconductor element, a first insulating layer, an acoustic wave element, a second insulating layer, a first intermediate layer, and a second intermediate layer. The first intermediate layer is interposed between the acoustic wave element and the semiconductor element, and has a thermal conductivity lower than the first and second insulating layers. The second intermediate layer is interposed between the first insulating layer and the second insulating layer, and has a thermal conductivity lower than the first and second insulating layers. A step is provided between a first principal surface of the first insulating layer and one principal surface of the semiconductor element. The distance between first and second principal surfaces of the first insulating layer is greater than the distance between the second principal surface of the first insulating layer and the one principal surface of the semiconductor element.

Terahertz device A1 includes first resin layer 21, columnar conductor 31, wiring layer 32, terahertz element 11, second resin layer 22, and external electrode 40. Resin layer 21 includes first resin layer obverse face 211 and first resin layer reverse face 212. Columnar conductor 31 includes first conductor obverse face 311 and first conductor reverse face 312, penetrating first resin layer 21 in z-direction. Wiring layer 32 spans between first resin layer obverse face 221 and first conductor obverse face 311. Terahertz element 11 includes element obverse face 111 and element reverse face 112, and converts between terahertz wave and electric energy. Second resin layer 22 includes second resin layer obverse face 221 and second resin layer reverse face 222, and covers wiring layer 32 and terahertz element 11. External electrode 40, disposed offset in a direction first resin layer reverse face 222 faces with respect to first resin layer 32, is electrically connected to columnar conductor 31. Terahertz element 11 is conductively bonded to wiring layer 32.

A module includes a substrate, a first component on a first main surface of the substrate and from which heat is to be dissipated, a sealing resin layer that encloses the first component, and a heat-dissipating member that includes a first and a second heat-dissipating portions. The first heat-dissipating portion is disposed in the sealing resin layer, spaced apart from an upper surfaces of the first component, and includes a first overlap portion that overlaps an upper surfaces of the first component when viewed in plan in a direction perpendicular to the first main surface. The second heat-dissipating portion extends from an undersurface of the first overlap portion to the upper surface of the first component. An area of the second heat-dissipating portion on a surface of the first overlap portion including the undersurface is smaller than an area of the first overlap portion.

A method for packaging a chip and a chip package structure are provided. The method is used to package the chip including an acoustic filter. The packaging substrate and the device wafer are welded together, wherein the edge of the device wafer is chamfered, the packaging substrate is provided with a groove, the chamfered portion of device wafer is aligned with the groove on the substrate, and then a mask is disposed. The surface of the mask facing the device wafer is an inclined surface, forming a wedge-shaped opening. A package resin material is printed, wherein the package resin material falls into the groove through the inclined surface of the mask, and a package resin film is formed between the groove and the chamfer. The mask is removed along the first surface toward the second surface. The package resin is cured in a position where the resin film is located.

A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body.

A method for manufacturing a semiconductor panel is disclosed. In one example, the method includes providing a first preformed polymer form. The method further includes arranging multiple semiconductor chips over the first preformed polymer form. The method further includes attaching a second preformed polymer form to the first preformed polymer form, wherein the semiconductor chips are arranged between the attached preformed polymer forms, and wherein the attached preformed polymer forms form the semiconductor panel encapsulating the semiconductor chips.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.