Provided is an adhesive for semiconductor mounting that can achieve high-precision gap control and can increase heat resistance when a semiconductor is mounted. An adhesive for semiconductor mounting according to the present invention is an adhesive that is used for mounting a semiconductor, and contains a silicone resin and a spacer, the content of the spacer being 0.1% by weight or more and 5% by weight or less in 100% by weight of the adhesive, the 10% compressive elasticity modulus of the spacer being 5000 N/mm.sup.2 or more and 15000 N/mm.sup.2 or less, and the average particle diameter of the spacer being 10 m or more and 200 m or less.

The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

An electronic device has a substrate 5, a first electric element 91 provided on a first conductor layer 71, a second electric element 92 provided on the first electric element 91, and a connector 50 having a base end part 45 provided on a second conductor layer 72 and a head part 40 provided on a front surface electrode 92a of the second electric element 92 via a conductive adhesive 75. An area of the base end part 45 placed on the second conductor layer 72 is larger than an area of the head part 40 placed on the second electric element 92. The base end part 45 is located at a side of the substrate 5 compared with the head part 40, and a gravity center position of the connector 50 is at a side of the base end part 45 of the connector 50.

The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

A semiconductor apparatus includes: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label flexible and arranged on the semiconductor package, the conductive label including: a first adhesive layer contacting the semiconductor package; a thermally-conductive layer attached to the semiconductor package by the first adhesive layer and having a second length in the first horizontal direction greater than the first length; and a second adhesive layer contacting a portion of a surface of the conductive layer, the portion not vertically overlapping the semiconductor package; a thermal interface material (TIM) arranged on the conductive layer to vertically overlap the semiconductor package; and a cover including: a first cover portion vertically overlapping the semiconductor package and contacting the TIM; and a second cover portion to which the thermally-conductive layer is attached by the second adhesive layer.

A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package, a first adhesive and a second adhesive. The substrate has a first board surface and a second board surface, and a second region surrounds a first region on the first board surface. The semiconductor package has an upper surface, a lower surface, and a side surface, and is disposed on the first board surface. The first adhesive is formed on the first board surface, in the second region and in a portion of the first region adjacent to the second region. The second adhesive is formed between the side surface and the first adhesive and contacts the side surface and the first adhesive, and the first adhesive and the second adhesive together form a pier adhesive.

An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90 and a connection body 50 having a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75. The head part 40 has a second projection protruding 42 toward the electronic element 95 and a first projection 41 protruding from the second projection 42 toward the electronic element 95.

A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.

The embodiments of the present disclosure provide a bonding device for a chip on film and a display panel and a bonding method for the same. The bonding device includes: a bearing stage having a horizontal bearing surface for supporting at least one row of display panels, wherein one row of the at least one row of display panels has a row of first bonding regions; a grasping unit disposed above the bearing stage and configured to grasp at least a partial area of the entire chip on film so that a row of second bonding regions of the entire chip on film is horizontally located above the one row of display panels; and a bonding unit configured to bond the row of second bonding regions which has been aligned with the row of first bonding regions to the row of first bonding regions.

A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.