A semiconductor device is provided, the semiconductor device having: a semiconductor chip; a wiring substrate which supports the semiconductor chip and is electrically connected to the semiconductor chip; a first metal plate which supports the wiring substrate; a second metal plate which is arranged between the wiring substrate and the first metal plate; a first bonding part which bonds the wiring substrate and the second metal plate; and a second bonding part which bonds the first metal plate and the second metal plate, and having a thickness of an outer circumferential part of the second metal plate being larger than a thickness of a center part of the second metal plate.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

Various embodiments provide an electronic module comprising a baseplate. A recess is formed in one main surface of the baseplate, wherein the recess is adapted to accommodate an electronic chip. The electronic chip is attached to a substrate or carrier and is placed in the recess.

A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.

A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.

Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

The semiconductor device A1 includes a support member 2, a metal part 30 having obverse and reverse surfaces 301-302 spaced in z direction, with the reverse surface 302 bonded to the support member 2, a second bonding layer 42 boding the support member 2 and the metal part 30, a semiconductor element 10 facing the obverse surface 301 and bonded to the metal part 30, and a sealing member 7 covering the support member 2, metal part 30, second bonding layer 42 and semiconductor element 10. The metal part 30 includes a first body 31 of a first material and a second body 32 of a second material, with a boundary between the bodies 31-32. The second material has a linear thermal expansion coefficient smaller than that of the first material. The semiconductor device is improved in reliability by reducing thermal stress from heat generation of the semiconductor element.

In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) formed in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate, and methods of making the same.

A lead frame includes an outer frame. The outer frame includes: one surface; another surface that is opposite to the one surface; a side surface between the one surface and the other surface; a recess that is formed to extend from the one surface to the side surface; and a notch step portion that is formed to extend from the other surface to the side surface.