A power semiconductor device is provided with a base plate thermally connected to the power semiconductor element for heat generated from the power semiconductor element to be conducted to heat radiation fins. An electrically conductive member fixed to the base plate is electrically conducted to the base plate and is connected to ground, and has projections fitted into notches provided in the electrically conductive member. By deforming the projections, the electrically conductive member is fixed to the base plate and electrical conduction can be secured. With this arrangement, noise radiated from the power semiconductor element is reduced and malfunction of the power semiconductor element is suppressed.

A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

A heat sink for cooling at least one power semiconductor module, and that includes a basin for containing a cooling liquid. The basin has a contact rim for receiving the base plate and that includes a surface that is sloped inwards to the basin.

A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

A package includes a conductor base plate having a element fixed to an upper surface thereof, a side wall provided on the conductor base plate to surround the element, the side wall having a conductor portion electrically connected to the conductor base plate, a dielectric cap disposed on the side wall, a front-side metal film provided on an outer surface of the dielectric cap, a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate, and a plurality of vias passing through the dielectric cap to achieve electrical connection between the front-side metal film and the first back-side metal film and between the front-side metal film and the conductor portion oldie side wall.

A joined body manufacturing method includes: a laminating step for forming a laminated body in which either a copper circuit substrate (first member) or a ceramic substrate (second member) is coated beforehand with a temporary fixing material the main ingredient of which is a saturated fatty acid, the copper circuit substrate and the ceramic substrate are stacked and positioned by the temporary fixing material which has been melted, and by cooling the temporary fixing material the stacked copper substrate and ceramic substrate are temporarily fixed; and a joining step for forming a joined body in which the copper circuit substrate and the ceramic substrate are joined by heating with pressurizing the laminated body in the stacking direction.

A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal molded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the molded body used according to the method for contacting are selected corresponding to the magnitude.

A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating plate, a first circuit plate and a second circuit plate, the first circuit plate provided in a main surface of the insulating plate to be electrically connected to the gate electrode, the second circuit plate provided in the main surface to surround the first circuit plate and to be electrically connected to the source electrode; a first terminal, being column-shaped and electrically and mechanically connected to the first circuit plate; and a second terminal which is provided with a cylindrical body portion and support portions, the body portion has a through hole into which the first terminal is inserted with a gap, the support portions disposed in end portions of the body portion and electrically and mechanically connected to the second circuit plate.