A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

In a method for producing an electronic part mounting substrate wherein an electronic part 14 is mounted on one major surface (a surface to which the electronic part 14 is to be bonded) of the metal plate 10 of copper, or aluminum or the aluminum alloy (when a plating film 20 of copper is formed on the surface), the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) is surface-machined to be coarsened so as to have a surface roughness of not less than 0.4 μm, and then, a silver paste is applied on the surface-machined major surface (or the surface-machined surface of the plating film 20 of copper) to arrange the electronic part 14 thereon to sinter silver in the silver paste to form a silver bonding layer 12 to bond the electronic part 14 to the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) with the silver bonding layer 12.

The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.

A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Provided is a bidirectional semiconductor package in which the number of processes for manufacturing the bidirectional semiconductor package is reduced. According to present application, a portion between one end and the other end of the buffer wire is in contact with the lower surface of the upper DBC substrate and heat generated by the semiconductor chip is transferred to the upper DBC substrate.

A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu.sub.6Sn.sub.5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu.sub.6Sn.sub.5 portion is in contact with the nickel film.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

A power module includes: an insulating layer; a first metallic plate disposed on the insulating layer; a first semiconductor chip disposed on the first metallic plate; a first adhesive insulating layer and a second adhesive insulating layer disposed on the first metallic plate; a first metallic land for main electrode wiring disposed on the first adhesive insulating layer; and a first metallic land for signal wiring disposed on the second adhesive insulating layer. There can be provided a power module having reduced cost, reduced warpage of the whole of a substrate, stabilized quality, and improved reliability; and a fabrication method for such a power module.