An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

A soldering structure configured for preventing solder overflow during soldering and a power module, may include a component to be soldered; and a metal layer having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area.

Provided is a semiconductor module comprising a power semiconductor chip, a base, an insulating substrate bonded to the base, a semiconductor chip bonded to the insulating substrate, and a case adhered to the base by means of an adhesive. The semiconductor module has a low variability but a high assembly quality and reliability enabling a decrease in stress between the case and an adhered portion of the base. The base includes a plate-like first material, and a second material coating the first material and having a linear coefficient of expansion greater than that of the first material. The case covers at least part of a side surface of the base and is adhered to the base at least on an upper surface of the base by means of the adhesive, and a linear expansion coefficient of the case is larger than the linear expansion coefficient of the first material.

A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773 C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as t.sub.I, and a thickness of each of the metal layers being denoted as t.sub.M, a value of t.sub.I/t.sub.M is greater than or equal to 4.3.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

A semiconductor device is provided with a first insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a first semiconductor element disposed on the metal layer on one face of the first insulated substrate, a second insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a second semiconductor element disposed on one of the metal layers of the second insulated substrate, and an encapsulant encapsulating the first semiconductor element and the second semiconductor element. The metal layer on the other face of the first insulated substrate and the metal layer on the other face of the second insulated substrate are exposed on a first flat surface of the encapsulant.

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.