A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A wiring substrate includes an electronic component mounting pad, an electrode pad arranged at an outer side of the electronic component mounting pad, a first insulation layer formed on the electronic component mounting pad and the electrode pad, an opening formed in the first insulation layer on the electronic component mounting pad, a connection hole formed in the first insulation layer on the electrode pad, and recess portions formed at the electronic component mounting pad in the opening and at the electrode pad in the connection hole, respectively.

A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.

A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

An LED module includes: a substrate having a main surface and a back surface which face in opposite directions from each other in a thickness direction; a first LED chip including a first electrode pad bonded to a surface facing the same direction as the main surface; a first wire having one end bonded to the first electrode pad; and a wiring pattern having a main surface electrode formed in the main surface, wherein the main surface electrode includes a first die pad portion which supports the first LED chip, and when viewed from the thickness direction, the first die pad portion includes a main pad portion to which the first LED chip is bonded and an auxiliary pad portion which protrudes from the main pad portion in a direction toward a position of the first electrode pad from the center position in the first LED chip.

A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Implementations of semiconductor packages may include: a first semiconductor die having a plurality of balls coupled to a first side thereof, a second semiconductor die, a lead frame having a die attach area on a first side of the lead frame, the die attach area containing an opening therethrough and one or more wire bonds. The first semiconductor die may be coupled to a backside of the second semiconductor die by an adhesive on a second side of the first semiconductor die opposing the first side. The second semiconductor die may be mechanically and electrically coupled to the lead frame through one or more wire bonds at the die attach area. The first semiconductor die may be positioned within the opening in the center of the lead frame.

An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes first and second conductive loops. A first voltage is induced between first and second ends of the first conductive loop in response to an external magnetic field that passes through the integrated circuit package. A second voltage is induced between third and fourth ends of the second conductive loop of the lead frame in response to the external magnetic field that passes through the integrated circuit package. The first conductive loop is coupled to the second conductive loop such that the first voltage between the first and second ends combined with the second voltage between the third and fourth ends substantially cancel.