An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first metal wire electrically connecting the power semiconductor element and the first lead frame, and a sealing body covering these components. The first lead frame includes a first inner lead having a connecting surface to which one end of the first metal wire is connected. Among surfaces of the sealing body, in a side surface, a resin inlet mark is formed in a side surface portion from which the first lead frame and the second lead frame do not project, the resin inlet mark being greater in surface roughness than another area. The resin inlet mark is formed opposite to a side where the first metal wire is positioned on the connecting surface when seen in the direction along the mounting surface.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

An integrated circuit (IC) device includes a pressure sensor die, a flexible gel covering a least a pressure-sensing region of the die, and a flexible diaphragm covering the gel. The IC device has encapsulant and a lid that define a cavity above the diaphragm. The lid has an aperture that enables proximate ambient air pressure outside the device to be sensed by the pressure-sensing region through the flexible diaphragm and the flexible gel. The diaphragm protects the gel material from potentially harmful ambient materials. The diaphragm may be a part of the lid.

A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced.

Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required customization, which is defined by a system's interconnecting scheme, is done during package assembly by creating appropriate connections using wire bonds on pads that are placed on the substrate and intentionally left open for purpose of customization. The wire bond links can be changed as required for a given system design.

A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.

A semiconductor device according to the present invention includes: a semiconductor element; a first metal body having a die pad to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad; a second metal body which has a wire bond pad connected to a signal electrode of the semiconductor element via a wire, and is provided on the same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; and a molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.