A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite. In one example, the antistatic die attach material has a resistivity between 10.sup.1 Ω.Math.cm and 10.sup.10 Ω.Math.cm.

A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

An electronic device includes: an electronic element having an element obverse surface and an element reverse surface spaced apart from each other in a first direction, the element obverse surface being provided with an obverse-surface electrode; a resin member having a resin reverse surface facing in a same direction as the element reverse surface, the resin member covering the electronic element; and an electrically conductive member supporting the electronic element and electrically connected to the electronic element. The electrically conductive member has a first exposed region, a second exposed region and a third exposed region each of which is exposed from the resin reverse surface. The resin member has a first resin side surface and a second resin side surface connected to each other and standing up from the resin reverse surface. As viewed in the first direction, the first exposed region is located at a corner portion where the first resin side surface and the second resin side surface are connected. As viewed in the first direction, the second exposed region is located side by side with the first exposed region in a second direction extending along the first resin side surface. The third exposed region is located between the first exposed region and the second exposed region in the second direction. As viewed in the first direction, the third exposed region has a larger area than each of the first exposed region and the second exposed region.

A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion; selectively etching part of the conductive portion; and applying solder resist to a bottom surface of the conductive portion.

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

A metal plate 1 to be a lead frame has a plating with Sn or Zn or a plating with various alloys containing these metals only on the side faces and half-etched faces 6, and a noble metal plating layer formed on the front surface as a surface on which a semiconductor device is to be mounted.

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

A sensor can comprise a sensor die with a first sensor surface and a second sensor surface opposite to the first sensor surface. The sensor can further comprise a die pad component with a first pad surface and a second pad surface opposite to the first pad surface, wherein the sensor die is vertically stacked with the die pad component, with the second sensor surface oriented toward the first pad surface. The sensor can further comprise a lead frame component with a first frame surface and a second frame surface opposite to the first frame surface, the die pad component is vertically stacked with the lead frame component, wherein the second pad surface is oriented toward the first frame surface, the second pad surface is isolated from the second frame surface, and the lead frame component is electrically connected to the sensor die.

A light emitting device includes a resin package and a light emitting element. The resin package has a cavity. The resin package includes first and second lead portions and a resin member. The first lead portion includes a first lead side surface and a lead recess portion that extends from the first lead side surface in a direction away from the second lead portion, with a part of the resin member being arranged within the lead recess portion. The light emitting element includes first and second electrodes that respectively face the first and second lead portions. The first electrode includes a first electrode side surface and an electrode recess portion that extends from the first electrode side surface in a direction away from the second electrode. The electrode recess portion is arranged at a position overlapping the lead recess portion in a plan view.