A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

A pre-molded substrate for semiconductor devices includes a sculptured electrically conductive (e.g., copper) laminar structure having spaces therein. The laminar structure includes one or more die pads having a first die pad surface configured to have semiconductor chips mounted thereon. A pre-mold material molded onto the laminar structure penetrates into the spaces therein and provides a laminar pre-molded substrate including the first die pad surface left exposed by the pre-mold material with the die pad(s) bordering on the pre-mold material. One or more stress-relief curved portions are provided at the periphery of one or more of the die pads. The stress-relief curved portions are configured to border on the pre-mold material over a smooth surface to effectively counter the formation of cracks in the pre-mold material as a result of the pre-molded substrate being bent.

A pre-molded substrate includes a sculptured, electrically conductive laminar structure having spaces therein. The laminar structure includes a die pad having a first die pad surface configured to mount a semiconductor chip. A pre-mold material molded onto the laminar structure penetrates into the spaces and provides a laminar pre-molded substrate with the first die pad surface left exposed. The peripheral edge of the die pad includes an alternation of first and second anchoring formations to the pre-mold material. The first anchoring formations counter first detachment forces inducing displacement of the die pad with respect to the pre-mold material in a first direction from the second die pad surface to the first die pad surface. The second anchoring formations counter second detachment forces inducing displacement of the die pad with respect to the pre-mold material in a second direction from the first die pad surface to the second die pad surface.

A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.

A semiconductor device module includes an application board, a plurality of semiconductor device packages disposed on the application board, each one of the semiconductor device packages including a semiconductor die, a leadframe including a plurality of leads, the leads including a spring support and a heat dissipation element, and an encapsulant embedding the semiconductor die and first portions of the leads, an external heatsink, and one or more thermally conductive interface layers disposed between the semiconductor device package and the heatsink.

A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

In examples, a method of manufacturing a transformer device comprises providing a first magnetic member and providing a laminate member containing primary and secondary transformer windings wound around an orifice extending through the laminate member. The method further comprises positioning a build up film abutting the laminate member. The method also comprises positioning at least a portion of a second magnetic member in the orifice. The method further comprises heat pressing at least one of the first and second magnetic members such that a distance between the first and second magnetic members decreases and such that the build-up film melts, thereby producing a transformer device.

In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.

A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.