A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

A device includes a relative temperature detector configured to determine a temperature difference between a device temperature sensed near a switch device and an ambient temperature sensed outside the switch device. The relative temperature detector is configured to generate a relative temperature output signal based on comparing the temperature difference to a relative temperature threshold. A power detector is configured to generate a power level signal based on comparing an indication of switch power of the switch device to a power threshold. The power level signal specifies whether the indication of switch power is above or below the power threshold. A thermal capacity control is configured to disable the switch device based on the power level signal specifying that the indication of switch power is above the power threshold and based on the relative temperature output signal indicating the temperature difference is above the relative temperature threshold.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.

A power semiconductor module arrangement includes a substrate including a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, the dielectric insulation layer being disposed between the first and second metallization layers. The arrangement further includes at least one first connection element mounted on the substrate, a housing having sidewalls, and at least one second connection element. Each second connection element includes a first part extending vertically through a sidewall of the housing, a second part coupled to a first end of the first part and protruding from the sidewall in a vertical direction, and a third part coupled to a second end of the first part opposite the first end. Each third part is detachably coupled to one of the at least one first connection element.

A package structure comprises: a plurality of metal parts, wherein each metal part is made of metal and each two adjacent metal parts are spaced apart by a gap being filled with an insulating material; a first insulating layer, disposed over a top of the plurality of metal parts and the top surface of a conductive element; and a first conductive layer, disposed over the first insulating layer, wherein a first conductive pattern electrically connects a first terminal of the conductive element to a first metal part through at least one first via disposed in the first insulating layer, wherein a bump is disposed in the first insulating layer and electrically connected to a second terminal of the conductive element.

Various embodiments of an integrated device package with integrated antennas are disclosed. In some embodiments, an antenna can be defined along a die pad of the package. In some embodiments, an antenna can be disposed in a first packaging component, and an integrated device die can be disposed in a second packaging component. The first and second packaging components can be stacked on one another and electrically connected. In some embodiments, a package can include one or a plurality of antennas disposed along a wall of a package body. The plurality of antennas can be disposed facing different directions from the package.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

According to an embodiment, a wireless device includes an interposer, a semiconductor chip, electrodes, and a slot antenna. The interposer includes conductive layers disposed at least at a side of a component mounting surface and a side of a reverse surface opposite to the component mounting surface. The semiconductor chip is mounted on the component mounting surface and includes a built-in transceiving circuit. The electrodes are disposed in a conductive layer disposed at the side of the reverse surface of the interposer so as to be electrically connected to an outside of the wireless device. At least a portion of the slot antenna is disposed in at least one of the conductive layers of the interposer. A shortest distance between an end in a width direction of the slot antenna and the electrodes is smaller than a sum of a minimum line width and a minimum line space of the interposer.

A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.

A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.