A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

The present invention relates to a structure of a composite lead frame generally having a die bonding layer and a solder layer and may further have an cohesive layer between the die bonding layer and the solder layer. The die bonding layer is made of flex substrate and the solder layer is made of traditional lead frame. Thus, the composite lead frame structure is suitable for the flip chip or wire bonding packaging process of LED and also suitable for semiconductor IC packaging process. It is good in electric and heat conductivity, and also with higher mechanical strength, resulting high pin counts and minimization of resulted IC.

A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.

A lead frame assembly includes a lead frame body, an encapsulant unit, and dicing positioning units. The lead frame body includes lead frame units, an outer frame portion extending around the lead frame units, and through holes formed on the outer frame portion. The encapsulant unit includes a lower encapsulating portion, and an upper encapsulating portion formed on the lower encapsulating portion. The dicing positioning units are respectively located at the through holes, and each includes an adhesive layer which partially fills a corresponding one of the through holes and which is formed with at least one dicing positioning hole. The dicing positioning units define at least one first dicing positioning line and at least one second dicing positioning line.

A “double-deck” semiconductor device includes a first semiconductor chip mounted to a first surface of a leadframe, with a first wire bonding pattern and a first mass of encapsulating material molded onto the first surface of the leadframe when the leadframe is in a first spatial orientation. The leadframe with the first semiconductor chip and the first wire bonding pattern encapsulated and thus protected by the first mass of encapsulating material is then turned over to a second spatial orientation. A second semiconductor chip is attached to the second surface of the leadframe, with a second wire bonding pattern and a second mass of encapsulating material, different from the first mass of encapsulating material molded onto the second surface of the leadframe.

A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of t.sub.press1>t.sub.cast1 and t.sub.press2>t.sub.cast1, where t.sub.press1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, t.sub.press2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and t.sub.cast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.

A semiconductor device includes: a single die pad made of a metal or metal alloy and having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view; a signal lead arranged between the ground leads; a plurality of leads arranged around the die pad in plan view; a semiconductor chip mounted on the second surface; bonding wires connecting a signal pad of the chip and the signal lead and connecting a ground pad of the chip and the ground leads; and a mold resin covering the die pad, the signal lead, the plurality of leads, the chip, and the bonding wires; wherein an interval between the signal lead and each of the ground leads is narrower than an interval between the plurality of leads.