A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.

A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively.

A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively.

A semiconductor package includes a connection structure having including a plurality of insulating layers and redistribution layers on the plurality of insulating layers. A semiconductor chip has connection pads connected to the redistribution layers, and an encapsulant encapsulates the semiconductor chip. A passive component is embedded in the connection structure and has connection terminals connected to the redistribution layer. The redistribution layers include a plurality of redistribution patterns, each disposed on the plurality of insulating layers and a plurality of redistribution vias each penetrating through the plurality of insulating layers and connected to the plurality of redistribution patterns. The plurality of redistribution vias include a plurality of blocking vias arranged to surround the passive component, and the plurality of redistribution patterns include a blocking pattern connected to adjacent blocking vias.

A semiconductor module includes a supporting substrate, a conductive substrate supported by the supporting substrate, a conductive bonding member provided between the supporting substrate and the conductive substrate, and a semiconductor element electrically bonded to an obverse surface of the conductive substrate and having a switching function. The conductive bonding member includes a metal base layer, a first layer, and a second layer. The first layer is provided between the base layer and the conductive substrate, and is in direct contact with the conductive substrate. The second layer is provided between the base layer and the supporting substrate, and is in direct contact with the supporting substrate.

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.

An electronic device includes a semiconductor die, a package structure enclosing the semiconductor die, and a conductive lead having first and second surfaces. The first surface has a bilayer exposed along a bottom side of the package structure, and the second surface is exposed along another side of the package structure. The bilayer includes first and second plated layers, the first plated layer on and contacting the first surface of the conductive lead and the second plated layer on and contacting the first plated layer and exposed along the bottom side of the package structure, where the first plated layer includes cobalt, and the second plated layer includes tin.

A semiconductor device includes a substrate and a chip. The substrate has a first conduction layer, a second conduction layer, and an isolation layer disposed between the first conduction layer and the second conduction layer. The first conductive layer has a first portion and a second portion spaced apart from the first portion, and each of the first portion and the second portion includes a main part and a plurality of extension parts extending from the main part. The chip is disposed on the extension parts of the first portion and the second portion of the first conductive layer.

Described examples include an apparatus having a first antenna and a second antenna formed in a first layer on a first surface of a multilayer package substrate, the multilayer package substrate having layers including patterned conductive portions and dielectric portions, the multilayer package substrate having a second surface opposite the first surface. The apparatus also has an isolation wall formed in the multilayer package substrate formed in at least a second and a third layer in the multilayer package substrate and a semiconductor die mounted to the first surface of the multilayer package substrate spaced from and coupled to the first antenna and the second antenna.

A semiconductor of an embodiment includes a lead frame including a first bed; a first post; a second post; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip, a first film thickness of the first bonding material portion being thinner than a second film thickness of the second bonding material portion; a first connector; a second bonding material; and a third bonding material.