A circuit module includes a substrate module including an upper main surface with a normal line extending in a vertical direction, an electronic component on the substrate module, and a bonding adhesive fixing the electronic component to the upper main surface. The electronic component includes a first electrode. The substrate module includes a second electrode on the right of the bonding adhesive. The first electrode is electrically connected to the second electrode through solder. A first recess recessed downward and including a bottom is in the upper main surface. An upper end of the second electrode is above the bottom. The first recess includes a first area on the left of a first electrode and overlapping the second electrode when viewed in the lateral direction. A material of the first recess is identical to a material of the upper main surface.

The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

A microelectronic device, in a fan-out fan-in chip scale package, has a die and an encapsulation material at least partially surrounding the die. Fan-out connections from the die extend through the encapsulation material and terminate adjacent to the die. The fan-out connections include wire bonds, and are free of photolithographically-defined structures. Fan-in/out traces connect the fan-out connections to bump bond pads. The die and at least a portion of the bump bond pads partially overlap each other. The microelectronic device is formed by mounting the die on a carrier, and forming the fan-out connections, including the wire bonds, without using a photolithographic process. The die and the fan-out connections are covered with an encapsulation material, and the carrier is subsequently removed, exposing the fan-out connections. The fan-in/out traces are formed so as to connect to the exposed portions of the fan-out connections, and extend to the bump bond pads.

A half-bridge having power connections and signal connections shaped from a leadframe, the signal connections electrically connected to semiconductor switching elements so that they can be switched by the signal connections, and the power connections are electrically connected to the switching elements in so that they switch an electrical power transmission between the power connections. The switching elements are embedded in a modular layer system including a contact-connection plane and a metallization for contact-connecting the switching elements, the signal connections and the power connections are arranged on a first surface of the substrate. The modular layer system, the signal connections and the power connections are potted with a potting compound, and external sections of the power connections and/or signal connections shaped in the leadframe extend out of the potting compound from a second surface orthogonal to the first surface, the external sections having ends that are perpendicular to the first surface.

A process for batch fabrication of circuit components is disclosed via simultaneously packaging multiple circuit component dice in a matrix. Each die has electrodes on its tops and bottom surfaces to be electrically connected to a corresponding electrical terminal of the circuit component it's packaged in. For each circuit component in the matrix, the process forms preparative electrical terminals on a copper substrate. Component dice are pick-and-placed onto the copper substrate with their bottom electrodes landing on corresponding preparative electrical terminal. Horizontal conductor plates are then placed horizontally on top of the circuit component dice, with bottom surface at one end of each plate landing on the dice's top electrode. An opening is formed at the opposite end and has vertical conductive surfaces. A vertical conductor block is placed into the opening and lands on the preparative electrical terminal, and the opening's vertical conductive surfaces facing the top end side surface of the vertical block. A thermal reflow then simultaneously melts pre-applied soldering material so that each circuit component die and its vertical conductor block are soldered to the copper substrate below and its horizontal conductor plate above.

A semiconductor device is provided, which includes a semiconductor chip; a first current input/output portion that is electrically connected to the semiconductor chip; a second current input/output portion that is electrically connected to the semiconductor chip; three or more conducting portions provided with the semiconductor chip, between the first current input/output portion and the second current input/output portion; and a current path portion having a path through which current is conducted to each of the three or more conducting portions, wherein the current path portion includes a plurality of slits.

Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the lead frame proximate to a geometric center of the lead frame may be rounded to include a radius of curvature of at least two times a greatest thickness of the die-attach pad. The thickness of the die-attach pad may be measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and each one of the lead fingers having a surface area larger than an average surface area of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

A first frame includes portions of a first short side surface and a first long side surface, in which a plurality of conductor layers to which a plurality of DC electrode terminals are connected, and a plurality of insulating layers arranged between the plurality of conductor layers are stacked. Further, a second frame includes portions of a second short side surface and a second long side surface.

A Faraday cage cavity package, having: a leadframe; a plastic body molded onto the leadframe to form a cavity exposing top surfaces of a die attach paddle, tie bars and lead fingers of the leadframe within the cavity; and a lid attached onto the top of the leadframe to protect a die attached to the die attach pad from electromagnetic fields, wherein the Faraday cage cavity package is manufactured in a matrix format and then separated into a plurality of individual Faraday cage cavity package units.

A light emitting device includes: a base body including two conductive members, a resin body, and a fiber member placed inside the resin body, and a light-emitting element. The resin body includes an isolation section located between the two conductive members, and includes a pair of sandwiching portions sandwiching the isolation section. The fiber member has a length which is greater than a distance between the two conductive members, and is located at least in an adjoining region of at least one of the pair of sandwiching portions, the adjoining region adjoining the isolation section. In the adjoining region, the fiber member extends in a direction which is non-orthogonal to a direction in which that the pair of sandwiching portions extend.