A semiconductor package includes a terminal pad having at least one first terminal lead structurally connected to the terminal pad, a semiconductor chip attached to an upper surface of the terminal pad by using a first adhesive, a heat radiation board attached to a lower surface of the terminal pad by using a second adhesive, and at least one second terminal lead electrically connected to the semiconductor chip. The second terminal lead is spaced apart from the terminal pad and is separated from the radiation board. The package further includes a metal clip electrically connecting the semiconductor chip to the second terminal lead, and a package housing covering parts of the first terminal lead, the second terminal lead, and the terminal pad. The package housing includes an adhesive spread space to expose the lower surface of the terminal pad.

A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.

Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

Radio frequency (RF) packages containing substrates having coefficient of thermal expansion (CTE) matched mount pads are disclosed, as are methods for fabricating RF packages and substrates. In embodiments, the RF package contains a high thermal performance substrate including a metallic base structure, which has a frontside facing a first RF power die and a first die attach region on the frontside of the base structure. A first CTE matched mount pad is bonded to the metallic base structure and covers the first die attach region. The first CTE mount pad has a CTE greater than the CTE of RF power die and less than the CTE of the metallic base structure. An electrically-conductive bonding material attaches the RF power die to the first CTE matched mount pad, while RF circuitry integrated into first RF power die is electrically coupled to the metallic base structure through the mount pad.

A semiconductor apparatus includes: a power semiconductor element; a control chip including a plurality of terminals including a first terminal and a second terminal, and being configured to control the power semiconductor element using a power supply voltage supplied to the second terminal; a first conductor for supplying a predetermined control voltage to the first terminal; a first line for supplying the power supply voltage to the second terminal; and semiconductor chip including a diode that is used for a bootstrap operation for generating the power supply voltage. The semiconductor chip includes: a semiconductor substrate: including a first face and a second face that are opposed to each other; and having a PN junction of the diode formed by a p-type semiconductor region on the first face and an n-type semiconductor region on the second face, an anode formed on the first face and joined to a surface of the first conductor, and a cathode formed on the second face and electrically connected to the second terminal via the first line.

In this power semiconductor module, a first lead frame and a second lead frame through which currents flow in opposite directions are arranged so as to overlap each other, whereby the internal inductance can be reduced. In a direction perpendicular to one main surface of a first metal wiring layer, each of the first lead frame and the second lead frame is provided so as not to overlap parts of end surfaces of the first metal wiring layer and a second metal wiring layer. Thus, in a manufacturing process for the power semiconductor module before sealing with sealing resin, it is possible to easily perform positioning between the lead frames and between the metal wiring layer and the lead frame, using the end surfaces, whereby the manufacturing process can be simplified.

A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

A semiconductor package includes: a carrier having a first side and a second side opposite the first side, the first side having a plurality of contact structures; a semiconductor die having a first side and a second side opposite the first side, the first side of the semiconductor die having a plurality of pads attached to the plurality of contact structures at the first side of the carrier; a metal plate attached to the second side of the semiconductor die, the metal plate having a size that is independent of the size of the carrier and based on an expected thermal load to be presented by the semiconductor die; and an encapsulant confined by the carrier and the metal plate and laterally surrounding an edge of the semiconductor die. Corresponding methods of production are also provided.