Patent classifications
H01L23/49575
Integrated circuit package with partitioning based on environmental sensitivity
An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.
Cooling apparatus, semiconductor module, and vehicle
A semiconductor module including a cooling apparatus and a semiconductor device mounted on the cooling apparatus is provided. The cooling apparatus includes a cooling fin arranged below the semiconductor device, a main-body portion flow channel through which a coolant flows in a predetermined direction to cool the cooling fin, a first coolant flow channel that is connected to one side of the main-body portion flow channel and has a first inclined portion upwardly inclined toward the main-body portion flow channel, and a conveying channel that, when seen from above, lets the coolant into the first coolant flow channel from a direction perpendicular to the predetermined direction or lets the coolant out of the first coolant flow channel in the direction perpendicular to the predetermined direction.
Packaged multichip module with conductive connectors
In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.
Cascode semiconductor
This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.
Microelectronic device with floating pads
A microelectronic device has a first die attached to a first die pad, and a second die attached to a second die pad. A magnetically permeable member is attached to a first coupler pad and a second coupler pad. A coupler component is attached to the magnetically permeable member. The first die pad, the second die pad, the first coupler pad, the second coupler pad, and the magnetically permeable member are electrically conductive. The first coupler pad is electrically isolated from the first die, from the second coupler pad, and from external leads of the microelectronic device. The second coupler pad is electrically isolated from the first die and from the external leads. The first die and the second die are electrically coupled to the coupler component. A package structure contains at least portions of the components of the microelectronic device and extends to the external leads.
Isolated transformer with integrated shield topology for reduced EMI
A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
Leads for semiconductor package
A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
Multi-chip module leadless package
A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.
Compact low inductance chip-on-chip power card
Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion. The O lead frame is located between the N lead frame and the P lead frame. The power card includes a first power device located between the N lead frame and the O lead frame, with a first side coupled to the body portion of the N lead frame and a second side coupled to the body portion of the O lead frame. The power card includes a second power device located between the O lead frame and the P lead frame, with a first side coupled to the body portion of the O lead frame and a second side coupled to the body portion of the P lead frame.
CONDUCTIVE METAL FRAME FOR A POWER ELECTRONIC MODULE AND ASSOCIATED MANUFACTURING PROCESS
A conductive metal frame for a power electronics module comprising at least first and second power semiconductor components each having upper and lower faces, connectors for linking these power semiconductor components to external electrical circuits and at least one radiator for expelling via the conductive metal frame the heat flow generated by the power semiconductor components, the conductive metal frame being characterized in that the connectors, the at least one radiator and the conductive metal frame forming a single three-dimensional part made of a single material on an inner surface of which the first and second power semiconductor components are intended to be attached by their lower faces and provision is made for a central folding line so that, once the conductive metal frame is folded on itself, enclosing the first and second power semiconductor components, it provides a double-sided cooling assembly.