A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described.

According to one embodiment, a semiconductor device includes a frame with a die pad and terminals extending from the die pad in a first direction. A groove is provided in an upper surface of the die pad. A semiconductor element is on the upper surface of the die pad but does not overlap the groove. A resin material covers the semiconductor element and is in the groove. The groove includes a bottom surface with an irregularity therein.

Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant encapsulating at least part of the electronic component and only part of the carrier so that another exposed part of the carrier is exposed with regard to the encapsulant. The exposed part of the carrier comprises an electric connection structure and a corrosion protection structure. One of the electric connection structure and the corrosion protection structure is selectively formed on only a sub-portion of the other one of the electric connection structure and the corrosion protection structure outside of the encapsulant.

Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame including a die attach pad and a plurality of leads; a die including a MEMs region defined by a plurality of trenches, the die electrically connected to the plurality of leads; and a mold compound covering portions of the die, the mold compound defining a cavity between a surface of the die and a surface of the mold compound, wherein the mold compound defines a vent.

A semiconductor device includes a semiconductor substrate and a metal structure in electrical contact with the semiconductor substrate. The metal structure has copper as a main component. An encapsulation layer includes a matrix material and a releasable copper corrosion inhibitor dispersed in the matrix material. The matrix material of the encapsulation layer at least partially covers the metal structure. A protective layer is at least partially on and in contact with a surface of the metal structure, and disposed between the metal structure and the encapsulation layer.

A semiconductor device includes at least one member that is partially sealed by a sealing material and has a part of thereof being exposed from the sealing material, a reversible temperature indicating material, and an irreversible temperature indicating material. Each of the reversible temperature indicating material and the irreversible temperature indicating material is provided on a surface of any one of the at least one member.

A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.

A first frame is supported by a heat sink plate, surrounds an unmounted region of the heat sink plate, contains a resin, and has a first surface. A second frame contains a resin, and has a second surface opposing the first surface. An external terminal electrode passes between the first surface and the second surface. An adhesive layer contains a resin, and includes a lower portion, an upper portion, and an intermediate portion. The lower portion connects the external terminal electrode and the first surface to each other. The upper portion connects the external terminal electrode and the second surface to each other. The intermediate portion is disposed within a through hole of the external terminal electrode, and connects the lower portion and the upper portion to each other.

A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.