A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively.

Methods, apparatuses and systems provide technology that includes a first transistor, a second transistor stacked on the first transistor, at least one electrical conductor that is positioned between the first and second transistors and electrically connected to the first and second transistors, and a busbar that is electrically connected to the first and second transistors through the at least one electrical conductor.

An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

Certain aspects of the present disclosure generally relate to a modular capacitor array, such as for an integrated circuit package, and methods for fabricating the same. One example integrated circuit package generally includes a package substrate, a semiconductor die disposed above the package substrate, and at least one modular capacitor array disposed below the package substrate. The modular capacitor array may be a pre-packaged array of capacitive elements, such as multi-layer ceramic capacitors (MLCCs).

An electronic package is provided. The electronic package includes an electronic component and a leadframe. The electronic component has a passive surface. The leadframe includes a first patterned part under the electronic component and configured to provide a power to the electronic component by the passive surface.

A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

A semiconductor device according to an embodiment of the disclosure includes a base, a semiconductor element, a first conductor, and a second conductor. The base has an outer edge including a first part, a second part, and a third part. The first part and the second part are substantially parallel to each other. The third part extends in a direction that intersects both of the first part and the second part. The semiconductor element is covered with the base. The first conductor is coupled to the semiconductor element, and protrudes to an outside of the base from the first part of the outer edge. The second conductor is coupled to the semiconductor element, and protrudes to the outside of the base from the third part of the outer edge.

An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.

A surface-mountable electrical device, an assembly including the surface-mountable electrical device, and a method for producing the surface-mountable electrical device is provided. The surface-mountable electrical device includes at least one electrical component which is a semiconductor component and which is intended for generating radiation, a control circuit for pulsed operation of the component, and a capacitor which is connected to the component electrically in series and which is configured for the pulsed energization of the component. The surface-mountable electrical device further includes a lead frame assembly having a plurality of different lead frames as a mounting platform for the component, the capacitor and the control circuit, wherein at least one of the different lead frames of the lead frame assembly is thinner than a further lead frame of the different lead frames and the lead frame assembly lies only partially in a mounting side of the device.

In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.