According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.

A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.

Improving motion sensor robustness utilizing a room-temperature-volcanizing (RTV) material via a solder resist dam is presented herein. A sensor package comprises: a first semiconductor die; a second semiconductor die that is attached to the first semiconductor die to form a monolithic die; and a substrate comprising a top portion and a bottom portion, in which the top portion comprises a plurality of solder resist dams, the monolithic die is attached to the top portion of the substrate via the RTV material being disposed in a defined area of the top portion of the substrate, and the bottom portion of the substrate comprises electrical terminals that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board.

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

A semiconductor device includes an electrically insulating substrate including a substrate main surface and a substrate back surface facing opposite to each other in a thickness direction and at least one substrate side surface facing a direction intersecting the thickness direction, a semiconductor element arranged at a side of the substrate main surface, a heat-dissipating conductive portion that is provided at a position overlapping with at least a portion of the semiconductor element when viewed from the thickness direction and is exposed from the substrate back surface, a sealing resin that seals the semiconductor element while covering the substrate main surface, and at least one wiring portion that is connected to the heat-dissipating conductive portion, extends from the heat-dissipating conductive portion to the substrate side surface while being exposed from the substrate back surface, and is exposed from the substrate side surface.

Provided is an electronic apparatus including an electronic part, a resin member that covers the electronic part, and a plurality of leads each electrically connected to the electronic part, the resin member including a first resin side surface facing one side in a first direction orthogonal to a thickness direction of the resin member, the plurality of leads including a plurality of first side exposed portions arranged along the first resin side surface, each of the plurality of first side exposed portions being exposed from the first resin side surface, each of the plurality of first side exposed portions including a first tapered portion becoming narrower toward the first resin side surface as viewed in the thickness direction, the first tapered portion including a first front surface that faces the same direction as the first resin side surface in the first direction and is flush with the first resin side surface.

A semiconductor device package includes a multi-layer substrate including a bottom layer and a top layer. One or more dies are mounted on and electrically coupled to the top layer of the substrate. An electromagnetic interference (EMI) shield encapsulates the substrate and the semiconductor dies. A first plurality of conductive stubs is positioned around edges of the top layer of the substrate. Each of the conductive stubs includes an edge portion having a first thickness and in contact with the EMI shield. A second plurality of conductive stubs is positioned around edges of the bottom layer of the substrate. Each of the second plurality of conductive stubs includes an edge portion having a second thickness less than the first thickness and in contact with the EMI shield.

A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.