A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

An electronic package structure is provided. The electronic package structure includes a first carrier, a first electronic component, a first optical channel, and a second electronic component. The first electronic component is disposed on or within the first carrier. The first optical channel is disposed within the first carrier. The first optical channel is configured to provide optical communication between the first electronic component and the second electronic component. The first carrier is configured to electrically connect the first electronic component.

An electrical package can include a substrate having a first side and a second side opposite the first side. One or more electrical components mounted to the substrate, and a plurality of electrically conductive interconnect members can be coupled to the second side of the substrate. At least one of the interconnect members can have an elongated shape with a length that is longer than a width. The interconnect member with the elongated shape positioned can be at or proximate one of the corners. The interconnect members can be arranged as a grid, with first interconnect members each occupying a single grid cell, and second interconnect members each occupying at least two grid cells. The second interconnect members can have a shape of two of the first interconnect members coupled by a bridge portion.

A semiconductor device includes: a first insulating circuit substrate; a first semiconductor chip mounted on a top surface of the first insulating circuit substrate; a printed circuit board arranged over the first insulating circuit substrate; a first external terminal inserted to the printed circuit board and having one end bonded to the top surface of the first insulating circuit substrate; and a first pin inserted to the printed circuit board and having one end bonded to a top surface of the first semiconductor chip, wherein the first insulating circuit substrate and the printed circuit board having warps complimentary to each other.

A semiconductor device includes: a case having an opening; a semiconductor element contained in the case; a control substrate which is disposed above the semiconductor element in the case and on which a control circuit to control the semiconductor element is disposed; a lid to cover the opening of the case; and a control terminal having one end portion connected to the control circuit disposed on the control substrate and the other end portion protruding out of the case. The control terminal has a bend in the case, and a side portion of the case or the lid is provided with a support capable of supporting the bend.

A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer in a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.