A semiconductor device includes a baseplate and a case which includes an external wall surrounding an internal space and a dividing wall extending in a first direction and separating the space into compartments. The dividing wall has a lower end fixed to the principal surface and includes, on a sidewall, a terrace positioned further away from the principal surface than the lower end and hanging out toward the space compared to the lower end in a second direction parallel to the principal surface and perpendicular to the first direction. A terminal's bonding part, to which a wire is bonded, is disposed on the terrace. A ratio of the wire's diameter to the bonding part's width in the first direction is set to ≤0.15, which prevents a situation where bonding power is not sufficiently applied to the bonding part during ultrasonic bonding of the wire, thus increasing the bonding strength.

Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.

There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.

A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.

A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Methods and apparatuses to provide a pin, a pin combination structure and a package body are described. A baffle structure is sleeved on the pin. The baffle structure is used to prevent a plastic packaging material from overflowing from a cavity that accommodates the plastic packaging material. The cavity is in a mold for packaging the package body.

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

A terminal structure includes a wiring layer, a protective insulation layer, an open portion, and a connection terminal. The protective insulation layer covers the wiring layer. The open portion extends through the protective insulation layer in a thickness-wise direction to expose part of an upper surface of the wiring layer. The connection terminal is formed on the wiring layer exposed from the open portion. The open portion includes a wall surface, a depression, and a projection. The wall surface extends downward from an upper surface of the protective insulation layer. The depression is depressed into the protective insulation layer from the wall surface toward an outer side of the open portion. The projection is formed under the depression, continuously with the depression, and projected from the depression into the open portion further inward than the wall surface in a plan view. The depression is filled with the connection terminal.

A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.