The invention relates to a multi-layer 3D foil package and to a method for manufacturing such a multi-layer 3D foil package. The 3D foil package has a foil substrate stack having at least two foil planes, wherein a first electrically insulating foil substrate is arranged in a first foil plane, and wherein a second electrically insulating foil substrate is arranged in a second foil plane, wherein the first foil substrate has a first main surface region on which at least one functional electronic component is arranged, wherein the second foil substrate has a cavity having at least one opening in the second main surface region, wherein the foil substrates within the foil substrate stack are arranged one above the other such that the functional electronic component arranged on the first foil substrate is arranged within the cavity provided in the second foil substrate.

A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Disclosed are a system-on-chip integrated packaging structure, a manufacturing method therefor and a three-dimensional stacked device. The system-on-chip integrated packaging structure includes: a substrate, a chip, a first electrical connection structure and a second electrical connection structure. A front surface of the substrate is provided with a recess and a via welding pad, and a back surface of the substrate is provided with a conductive via extending to the via welding pad. The chip is embedded in the recess, and a chip welding pad is disposed on a surface of the chip away from a bottom surface of the recess. Different chips may be electrically connected by means of the first electrical connection structure and the second electrical connection structure, which is conducive to form a three-dimensional stacked structure with high-density interconnection, miniaturized packaging and thinning.

A flexible sensing device includes a flexible substrate selected from a bismaleimide-triazine resin substrate, an ajinomoto build-up film substrate, and a polyimide film substrate. A plurality of first sensing stripes are formed on the flexible substrate and are spaced apart from each other in a first direction. A dielectric film is superposed on the first sensing stripes. A plurality of second sensing stripes are formed on the dielectric film and are spaced apart from each other in a second direction. Each second sensing stripe crosses over the first sensing stripes and is spaced apart from the first sensing stripes by the dielectric film. A method of making the same is also disclosed.

Disclosed are wiring substrates, methods of fabricating the same, and methods of fabricating semiconductor packages. The wiring substrate includes a dielectric layer that includes a plurality of unit regions, a sawing region that surrounds each of the unit regions, and an edge region that surrounds the unit regions and the sawing region, a first upper protection pattern on a top surface of the dielectric layer on the unit regions and the sawing region, and a second upper protection pattern on a top surface of the dielectric layer on the edge region. The second upper protection pattern surrounds the first upper protection pattern when viewed in plan and includes a dielectric material different from a dielectric material of the first upper protection pattern.

A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.

A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.

The present invention includes a method of making a thermal management and signal control structure comprising forming in a substrate heat conductive vias and control vias, power vias, and ground vias, wherein the heat conductive vias and the control vias, power vias, and vias are aligned to a first metal plate on a first side of the substrate, wherein the control vias, power vias, and ground vias are surrounded by a glass layer; forming a second metal plate on a second side of the substrate, wherein the second metal plate is connected to the heat conductive vias; and forming a pad on each of the control vias, power vias, and ground vias, wherein each pad is configured to electrically connect the thermal management and signal control structure to at least one of: a printed circuit board, an integrated circuit, or a power management unit.