Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.

An electronic package including a middle patterned conductive layer, a first redistribution circuitry disposed on a first surface of the middle patterned conductive layer and a second redistribution circuitry disposed on a second surface of the middle patterned conductive layer is provided. The middle patterned conductive layer has a plurality of middle conductive pads. The first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements. Each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section. The second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements. Each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section.

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.