A wiring board includes: an insulating layer; and a connection terminal formed on the insulating layer. The connection terminal includes a first metal layer laminated on the insulating layer, a second metal layer laminated on the first metal layer, a metal pad laminated on the second metal layer, and a surface treatment layer that covers an upper surface and a side surface of the pad and that is in contact with the upper surface of the insulating layer. An end portion of the second metal layer is in contact with the surface treatment layer, and an end portion of the first metal layer is positioned closer to a center side of the pad than the end portion of the second metal layer is to form a gap between the end portion of the first metal layer and the surface treatment layer.

A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

The present disclosure relates to a transition system, which includes a monolithic microwave integrated circuit (MMIC) package and a printed-circuit-board (PCB) with a number of PCB vias. The MMIC package has a laminate-based body, which includes a substrate integrated waveguide (SIW) structure with a number of SIW vias, and a MMIC die over the laminate-based body. Herein, the SIW structure faces the PCB and is separate from the PCB with a gap in between. The SIW structure is configured to radiate radio frequency (RF) signals received from the MMIC die to the PCB. An arrangement of the PCB vias is scaling-mirrored to an arrangement of the SIW vias, such that each PCB via and a corresponding SIW via have a same relative position. The arrangement of PCB vias is about aligned with the arrangement of the SIW vias.

Embodiments described herein may be related to apparatuses, processes, and techniques related to a vertical high-speed bridge placed within a BGA field of a microelectronic package. In embodiments, the bridge is used for high-speed signaling and may include plated through hole vias that are at a smaller pitch than the pitch of the BGA field. In embodiments, the vertical high-speed bridge may be constructed from a glass wafer or a glass panel using a laser-assisted etching of glass interconnects process. Other embodiments may be described and/or claimed.

A glass wiring board that can be kept from cracking by better preventing concentration of stresses in a glass plate on which a conductor layer including an electrolytic copper plating layer is provided, the wiring board includes: a glass plate; a first metal layer covering at least a part of the glass plate; and a second metal layer covering at least a part of the first metal layer, and the area of the first metal layer in contact with the second metal layer is smaller than the area of the second metal layer facing the first metal layer.

Various aspects of this disclosure provide a method of manufacturing an electronic device and an electronic device manufactured thereby. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing an electronic device, and an electronic device manufactured thereby, that utilizes ink to form an intermetallic bond between respective conductive interconnection structures of a semiconductor die and a substrate.

A semiconductor package structure having an antenna module includes: a substrate, having a first surface and a second surface; a semiconductor chip, disposed on the first surface; a plastic packaging material layer, formed on the first surface, where the plastic packaging material layer wraps the semiconductor chip and exposes a part of a front surface of the semiconductor chip; a rewiring layer, disposed on the plastic packaging material layer and electrically connected to the semiconductor chip; a metal bump, electrically connected to the rewiring layer; and an antenna module, disposed on the second surface of the substrate.

In an embodiment of the present disclosure, a wiring base includes an insulative base, a signal conductor, a first lead terminal, a first ground conductor, and a second lead terminal. The insulative base includes a first face and a second face. The signal conductor is provided on the first face. The first lead terminal is provided on the signal conductor. The first lead terminal extends in a first direction and includes a portion projecting from the insulative base in plan view toward the first face. The first ground conductor is provided on the second face. The second lead terminal is provided on the first ground conductor. At least a part of the second lead terminal overlaps the first lead terminal in the plan view toward the first face.

A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.

The present disclosure relates to a flip-chip and a chip packaging structure. The flip-chip includes: a driver chip having a package surface facing a wiring substrate; and a plurality of conductive connectors. Any one of the plurality of conductive connectors includes a conductive bump connected to the package surface and a conductive extension portion on a side of the conductive bump away from the driver chip.