A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

A substrate debonding apparatus configured to separate a support substrate attached to a first surface of a device substrate by an adhesive layer, the substrate debonding apparatus including a substrate chuck configured to support a second surface of the device substrate, the second surface being opposite to the first surface of the device substrate; a light irradiator configured to irradiate light to an inside of the adhesive layer; and a mask between the substrate chuck and the light irradiator, the mask including an opening through which an upper portion of the support substrate is exposed, and a first cooling passage or a second cooling passage, the first cooling passage being configured to provide a path in which a coolant is flowable, the second cooling passage being configured to provide a path in which air is flowable and to provide part of the air to a central portion of the opening.

The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.

After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.